Datasheet

Electrical Specifications
18 Datasheet
3.2.3 FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.
3.3 Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the
Intel(R) IMVP-6 Mobile Processor Voltage Regulation Specification. The voltage set by
the VID signals is the reference VR output voltage to be delivered to the processor V
CC
pins. Refer to Table 13 for the DC specifications for these signals. Voltages for each
processor frequency is provided in Table 5.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 5.
The processor uses seven voltage identification signals, VID[6:0], to support automatic
selection of power supply voltages. Table 2 specifies the voltage level corresponding to
the state of VID[6:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to
a low voltage level. If the processor socket is empty (VID[6:0] = 1111111), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
CC
). This will represent a DC shift in the load
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 5 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 6 and Figure 2 as measured across the VCC_SENSE and VSS_SENSE pins.
The VRM or VRD used must be capable of regulating its output to the value defined by
the new VID. DC specifications for dynamic VID transitions are included in Table 5 and
Table 6. Refer to the Intel(R) IMVP-6 Mobile Processor Voltage Regulation Specification
for further details.
=
Table 2. Voltage Identification Definition (Sheet 1 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 V
CC
(V)
00 000 0 01.5000
00 000 0 11.4875
00 000 1 01.4750
00 000 1 11.4625
00 001 0 01.4500
00 001 0 11.4375
00 001 1 01.4250
00 001 1 11.4125
00 010 0 01.4000
00 010 0 11.3875
00 010 1 01.3750