Datasheet

Electrical Specifications
28 Datasheet
NOTES:
1. Refer to Chapter 4 for signal descriptions and termination requirements.
2. In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3. BPM[2:1]# and PRDY# are GTL+ output only signals.
4. PROCHOT# signal type is open drain output and CMOS input.
5. On die termination differs from other GTL+ signals.
6. When paired with a chipset limited to 32-bit addressing, A[35:32] should remain
unconnected.
Table 8. FSB Pin Groups
Signal Group Type Signals
1
GTL+ Common Clock Input
Synchronous
to BCLK[1:0]
BPRI#, DEFER#, PREQ#
5
, RESET#, RS[2:0]#,
DPWR#, TRDY#
GTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#
3
, BR0#, DBSY#,
DRDY#, HIT#, HITM#, LOCK#, PRDY#
3
GTL+ Source Synchronous
I/O
Synchronous
to Associated
Strobe
GTL+ Strobes
Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input Asynchronous
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output Asynchronous FERR#, IERR#, THERMTRIP#
Open Drain I/O Asynchronous PROCHOT#
4
CMOS Output Asynchronous PSI#, VID[6:0], BSEL[2:0]
CMOS Input
Synchronous
to TCK
TCK, TDI, TMS, TRST#
Open Drain Output
Synchronous
to TCK
TDO
FSB Clock Clock BCLK[1:0]
Power/Other
COMP[3:0], DBR#
2
, GTLREF, RSVD, TEST2,
TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP,
VCC_SENSE, VSS, VSS_SENSE
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[35:17]#
6
ADSTB[1]#
D[15:0]#, DINV0# DSTBP0#, DSTBN0#
D[31:16]#, DINV1# DSTBP1#, DSTBN1#
D[47:32]#, DINV2# DSTBP2#, DSTBN2#
D[63:48]#, DINV3# DSTBP3#, DSTBN3#