Datasheet

Electrical Specifications
30 Datasheet
3.8.3 Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads),
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
3. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
4. V
IH
and V
OH
may experience excursions above V
CCP
.
5. The V
CCP
referred to in these specifications is the instantaneous V
CCP
.
6. Leakage to V
SS
with pin held at V
CCP
.
7. Leakage to V
CCP
with pin held at 300 mV.
NOTES:
1. Measured at 0.2 V.
2. V
OH
is determined by value of the external pul-lup resistor to V
CCP
.
3. For Vin between 0 V and V
OH
.
4. C
PAD
includes die capacitance only. No package parasitics are included.
Table 11. GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
1
V
IL
Input Low Voltage -0.10 GTLREF – 0.10 V 2, 5
V
IH
Input High Voltage GTLREF + 0.10 V
CCP
+ 0.10 V 3, 4, 5
V
OH
Output High Voltage V
CCP
– 0.10 V
CCP
V4, 5
I
OL
Output Low Current N/A
V
CCP_MAX
/
[(R
TT_MIN
)+(R
ON_MIN
)]
A-
I
LI
Input Leakage Current N/A ± 100 µA 6
I
LO
Output Leakage Current N/A ± 100 µA 7
R
ON
Buffer On Resistance 10 13 Ω
Table 12. Open Drain and TAP Output Signal Group DC Specifications
Symbol Parameter Min Typ Max Unit Notes
1
V
OL
Output Low Voltage 0 — 0.20 V
I
OL
Output Low Current 16 — 50 mA 1
I
LO
Output Leakage Current — — ±200 µA 3
C
PAD
Pad Capacitance 1.9 2.2 2.45 pF 4