Datasheet

R
10 Specification Update
Steppings
NO.
B0 C1 D1
Plans ERRATA
V15 X Fixed
Incorrect data may be returned when page tables are in Write
Combining (WC) memory space
V16 X
X X
NoFix
Processor issues inconsistent transaction size attributes for locked
operation
V17 X Fixed
Multiple accesses to the same S-state L2 cache line and ECC error
combination may result in loss of cache coherency
V18 Fixed Processor may hang when resuming from Deep Sleep state
V19 X X X NoFix
When the processor is in the System Management Mode (SMM),
debug registers may be fully writeable
V20 X X X NoFix
Associated counting logic must be configured when using Event
Selection Control (ESCR) MSR
V21 X X X NoFix
IA32_MC0_ADDR and IA32_MC0_MISC Registers Will Contain
Invalid or Stale Data Following a Data, Address, or Response Parity
Error
V22 X Fixed
CR2 May Be Incorrect or an Incorrect Page Fault Error Code May Be
Pushed Onto Stack After Execution of an LSS Instruction
V23 X Fixed
BPM[5:3]# and GHI# V
IL
Do Not Meet Specification
V24 X
X X
NoFix
Processor May Hang Under Certain Frequencies and 12.5%
STPCLK# Duty Cycle
V25 X X X NoFix
System May Hang if a Fatal Cache Error Causes Bus Write Line
(BWL) Transaction to Occur to the Same Cache Line Address as an
Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL)
V26 X Fixed
L2 Cache May Contain Stale Data in the Exclusive State
V27 X
X
Fixed
Re-mapping the APIC Base Address to a Value Less Than or Equal to
0xDC001000 may Cause IO and Special Cycle Failure
V28 X
X
Fixed
Erroneous BIST Result Found in EAX Register After Reset
V29 X Fixed
Processor Does not Flag #GP on Non-zero Write to Certain MSRs
V30 X X X NoFix
Simultaneous Assertion of A20M# and INIT# may Result in Incorrect
Data Fetch
V31 X X X PlanFix Processor Does not Respond to Break Requests From ITP
V32 X Fixed Processor Signature Returns Incorrect Number of ITLB Entries
V33 X X X NoFix
A Write to APIC Registers Sometimes May Appear to Have Not
Occurred
V34 X Fixed Store to Load Data Forwarding may Result in Switched Data Bytes
V35 X X X NoFix Parity Error in the L1 Cache may Cause the Processor to Hang
V36 X X Fixed
The TCK Input in the Test Access Port (TAP) is Sensitive to Low
Clock Edge Rates and Prone to Noise Coupling Onto TCK’s Rising or
Falling Edges
V37 X X X NoFix
The State of the Resume Flag (RF Flag) in a Task-State Segment
(TSS) May be Incorrect
V38 X X X NoFix
Changes to CR3 Register do not Fence Pending Instruction Page
Walks
V39 X X X NoFix
System Bus Interrupt Messages without Data that Receive a