Datasheet

R
Specification Update 11
Steppings
NO.
B0 C1 D1
Plans ERRATA
HardFailure Response May Hang the Processor
V40 X X X NoFix
Memory Type of the Load Lock Different from its Corresponding Store
Unlock
V41 X X X NoFix
A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call)
May Cause an Incorrect Address to Be Reported to the #GP Exception
Handler
V42 X X X NoFix
Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint
is set on an FP Instruction
V43 X X X NoFix xAPIC May Not Report Some Illegal Vector Errors
V44 X X X NoFix
Memory Aliasing of Pages as Uncacheable Memory Type and Write
Back (WB) May Hang the System
V45 X Plan Fix
A Timing Maginality in the Arithmetic Logic Unit (ALU) May Cause
Indeterminate Behavior
V46 X X X No Fix
With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap Before
Retirement of Instruction
V47 X X X No Fix
BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling)
May Update Memory outside the BTS/PEBS Buffer
V48 X X X No Fix
Memory Ordering Failure May Occur with Snoop Filtering Third-Party
Agents after Issuing and Completing a BWIL (Bus Write Invalidate
Line) or BLW (Bus Locked Write) Transaction
V49 X X X No Fix
Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS
Instruction with Fast Strings Enabled
V50 X X X No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May
Cause an Unexpected Interrupt
Number SPECIFICATION CHANGE
V1 Context ID feature added to CPUID Feature/IA32_MISC_Enable Registers
V2 BR0# Maximum Hold Time Specification Change
Number SPECIFICATION CLARIFICATIONS
V1 Clarifying DBI# Definition for all Processors with Intel NetBurst
®
Microarchitecture
V2 Specification Clarification with respect to Time-stamp Counter
Number DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.