Datasheet

R
Specification Update 21
V13.
EMON Event Counting of x87 Loads May Not Work As Expected
Problem: If a performance counter is set to count x87 loads and floating point exceptions are unmasked, the FPU
Operand Data Pointer (FDP) may become corrupted.
Implication: When this erratum occurs, the FPU Operand Data Pointer (FDP) may become corrupted.
Workaround: This erratum will not occur with floating point exceptions masked. If floating point exceptions are
unmasked, then performance counting of x87 loads should be disabled.
Status: For the steppings affected, see the Summary Tables of Changes.
V14. Speculative Page Fault May Cause Livelock
Problem: If the processor detects a page fault which is corrected before the operating system page fault handler
can be called e.g. DMA activity modifies the page tables and the corrected page tables are left in a non-
accessed or not dirty state, the processor may livelock. Intel has not been able to reproduce this erratum
with commercial software.
Implication: Should this erratum be encountered the processor will livelock resulting in a system hang or operating
system failure.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
V15.
Incorrect Data May be Returned When Page Tables Are in Write Combining
Memory (WC) Space
Problem: If page directories and/or page tables are located in Write Combining (WC) memory, speculative loads
to cacheable memory may complete with incorrect data.
Implication: Cacheable loads to memory mapped using page tables located in write combining memory may return
incorrect data. Intel has not been able to reproduce this erratum with commercially available software.
Workaround: Do not place page directories and/or page tables in WC memory.
Status: For the steppings affected, see the Summary Tables of Changes.
V16.
Processor Issues Inconsistent Transaction Size Attributes for Locked Operation
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access
and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto
the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Correct data is provided since only the lower bytes change, however external logic monitoring the data
transfer may be expecting an 8 byte store unlock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.