Datasheet

R
22 Specification Update
V17.
Multiple Accesses to the Same S-State L2 Cache Line and ECC Error
Combination May Result in Loss of Cache Coherency
Problem: When a Read for Ownership (RFO) cycle has a 64 bit address match with an outstanding read hit on a
line in the L2 cache which is in the S-state AND that line contains an ECC error, the processor should
recycle the RFO until the ECC error is handled. Due to this erratum, the processor does not recycle the
RFO and attempts to service both the RFO and the read hit at the same time.
Implication: When this erratum occurs, cache may become incoherent.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
V18.
Processor May Hang When Resuming from Deep Sleep State
Problem: When resuming from the Deep Sleep state the address strobe signals (ADSTB[1:0]#) may become out of
phase with respect to the system bus clock (BCLK).
Implication: When this erratum occurs, the processor will hang.
Workaround: The system BIOS should prevent the processor from going to the Deep Sleep state.
Status: For the steppings affected, see the Summary Tables of Changes.
V19.
When the Processor Is in the System Management Mode (SMM), Debug
Registers May Be Fully Writeable
Problem: When in System Management Mode (SMM), the processor executes code and stores data in the
SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor
should block writes to the reserved bit locations. Due to this erratum, the processor may not block these
writes. This may result in invalid data in the reserved bit locations.
Implication: Reserved bit locations within DR6 and DR7 may become invalid.
Workaround: Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the values in
the reserved bits are maintained.
Status: For the steppings affected, see the Summary Tables of Changes.