Datasheet

R
Specification Update 23
V20.
Associated Counting Logic Must Be Configured When Using Event Selection
Control (ESCR) MSR
Problem: ESCR MSRs allow software to select specific events to be counted, with each ESCR usually associated
with a pair of performance counters. ESCRs may also be used to qualify the detection of at-retirement
events that support precise-event-based sampling (PEBS). A number of performance metrics that support
PEBS require a 2nd ESCR to tag uops for the qualification of at-retirement events. (The first ESCR is
required to program the at-retirement event.) Counting is enabled via counter configuration control
registers (CCCR) while the event count is read from one of the associated counters. When counting
logic is configured for the subset of at-retirement events that require a 2nd ESCR to tag uops, at least one
of the CCCRs in the same group of the 2nd ESCR must be enabled.
Implication: If no CCCR/counter is enabled in a given group, the ESCR in that group that is programmed for tagging
uops will have no effect. Hence a subset of performance metrics that require a 2nd ESCR for tagging
uops may result in 0 count.
Workaround: Ensure that at least one CCCR/counter in the same group as the tagging ESCR is enabled for those
performance metrics that require two ESCRs and tagging uops for at-retirement counting.
Status: For the steppings affected, see the Summary Tables of Changes.
V21.
IA32_MC0_ADDR and IA32_MC0_MISC Registers Will Contain Invalid or Stale
Data Following a Data, Address, or Response Parity Error
Problem: If the processor experiences a data, address, or response parity error, the ADDRV and MISCV bits of the
IA32_MC0_STATUS register are set, but the IA32_MC0_ADDR and IA32_MC0_MISC registers are
not loaded with data regarding the error.
Implication: When this erratum occurs, the IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid
or stale data.
Workaround: Ignore any information in the IA32_MC0_ADDR and IA32_MC0_MISC registers after a data, address
or response parity error.
Status: For the steppings affected, see the Summary Tables of Changes.
V22.
CR2 May Be Incorrect or an Incorrect Page Fault Error Code May Be Pushed
onto Stack After Execution of an LSS Instruction
Problem: Under certain timing conditions, the internal load of the selector portion of the LSS instruction may
complete with potentially incorrect speculative data before the load of the offset portion of the address
completes. The incorrect data is corrected before the completion of the LSS instruction but the value of
CR2 and the error code pushed on the stack are reflective of the speculative state. Intel has not observed
this erratum with commercially available software.
Implication: When this erratum occurs, the contents of CR2 may be off by two, or an incorrect page fault error code
may be pushed onto the stack.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.