Datasheet

24 Specification Update

V23.

BPM[5:3]# and GHI# VIL Does Not Meet Specification

Problem: The V

for BPM[5:3]# and GHI# is specified as 0.9 * GTLREF [V]. Due to this erratum the V

for

these signals is 0.9 * GTLREF - .075 [V].

Implication: The processor requires a lower input voltage than specified to recognize a low voltage on the BPM[5:3]#

and GHI# signals.

Workaround: When intending to drive the BPM[5:3]# or GHI# signals low, ensure that the system provides a voltage

lower than 0.9 * GTLREF - .075 [V].

Status: For the steppings affected, see the Summary Tables of Changes.

V24.

Processor May Hang Under Certain Frequencies and 12.5% STPCLK# Duty

Cycle

Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, the processor is running below 2 GHz, and the

processor thermal control circuit (TCC) on-demand clock modulation is active, the processor may hang.

This erratum does not occur under the automatic mode of the TCC.

Implication: When this erratum occurs, the processor will hang.

Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK#

modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle.

Status: For the steppings affected, see the Summary Tables of Changes.

V25.

System May Hang If a Fatal Cache Error Causes Bus Write Line (BWL)

Transaction to Occur to the Same Cache Line Address as an Outstanding Bus

Read Line (BRL) or Bus Read-Invalidate Line (BRIL)

Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL transaction to

the same cache line address as an outstanding BRL or BRIL. As it is not typical behavior for a single

processor to have a BWL and a BRL/BRIL concurrently outstanding to the same address, this may

represent an unexpected scenario to system logic within the chipset.

Implication: The processor may not be able to fully execute the machine check handler in response to the fatal cache

error if system logic does not ensure forward progress on the system bus under this scenario.

Workaround: System logic should ensure completion of the outstanding transactions. Note that during recovery from

a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL transactions is

not important. Forward progress is the primary requirement.

Status: For the steppings affected, see the Summary Tables of Changes.