Datasheet

Specification Update 25

V26.

L2 Cache May Contain Stale Data in the Exclusive State

Problem: If a cacheline (A) is in Modified (M) state in the write-combining (WC) buffers and in the Invalid (I)

state in the L2 cache and its adjacent sector (B) is in the Invalid (I) state and the following scenario

occurs:

1. A read to B misses in the L2 cache and allocates cacheline B and its associated second-sector pre-

fetch into an almost full bus queue,

2. A Bus Read Line (BRL) to cacheline B completes with HIT# and fills data in Shared (S) state,

The bus queue full condition causes the prefetch to cacheline A to be cancelled, cacheline A will remain

M in the WC buffers and I in the L2 while cacheline B will be in the S state.

Then, if the further conditions occur:

1. Cacheline A is evicted from the WC Buffers to the bus queue which is still almost full,

2. A hardware prefetch Read for Ownership (RFO) to cacheline B, hits the S state in the L2 and

observes cacheline A in the I state, allocates both cachelines,

3. An RFO to cacheline A completes before the WC Buffers write modified data back, filling the L2

with stale data,

4. The writeback from the WC Buffers completes leaving stale data, for cacheline A, in the

Exclusive (E) state in the L2 cache.

Implication: Stale data may be consumed leading to unpredictable program execution. Intel has not been able to

reproduce this erratum with commercial software.

Workaround: It is possible for BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

V27.

Re-mapping the APIC Base Address to a Value Less Than or Equal to

0xDC001000 May Cause IO and Special Cycle Failure

Problem: Remapping the APIC base address from its default can cause conflicts with either I/O or special cycle

bus transactions.

Implication: Either I/O or special cycle bus transactions can be redirected to the APIC, instead of appearing on the

front-side bus.

Workaround: Use any APIC base addresses above 0xDC001000 as the relocation address.

Status: For the steppings affected, see the Summary Tables of Changes.