Datasheet

R
26 Specification Update
V28.
Erroneous BIST Result Found in EAX Register after Reset
Problem: The processor may show an erroneous BIST (built-in self test) result in the EAX register bit 0 after reset.
Implication: When this erratum occurs, an erroneous BIST failure will be reported in the EAX register bit 0, however
this failure can be ignored since it is not accurate.
Workaround: It is possible for BIOS to workaround this issue by masking off bit 0 in the EAX register where BIST
results are written.
Status: For the steppings affected, see the Summary Tables of Changes.
V29.
Processor Does Not Flag #GP on Non-Zero Write to Certain MSRs
Problem: When a non-zero write occurs to the upper 32 bits of IA32_CR_SYSENTER_EIP or
IA32_CR_SYSENTER_ESP, the processor should indicate a general protection fault by flagging #GP.
Due to this erratum, the processor does not flag #GP.
Implication: The processor unexpectedly does not flag #GP on a non-zero write to the upper 32 bits of
IA32_CR_SYSENTER_EIP or IA32_CR_SYSENTER_ESP. No known commercially available
operating system has been identified to be affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
V30.
Simultaneous Assertion of A20M# and INIT# May Result in Incorrect Data Fetch
Problem: If A20M# and INIT# are simultaneously asserted by software, followed by a data access to the
0xFFFFFXXX memory region, with A20M# still asserted, incorrect data will be accessed. With A20M#
asserted, an access to 0xFFFFFXXX should result in a load from physical address 0xFFEFFXXX.
However, in the case of A20M# and INIT# being asserted together, the data load will actually be from
the physical address 0xFFFFFXXX. Code accesses are not affected by this erratum.
Implication: Processor may fetch incorrect data, resulting in BIOS failure.
Workaround: Deasserting and reasserting A20M# prior to the data access will workaround this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
V31.
Processor Does Not Respond to Break Requests from ITP
Problem: On power-up and low-power state transitions, the processor’s TAP circuitry may remain in the Tap-
Logic-Reset(TLR) state.
Implication: The ITP is unable to cause a break on reset in the processor, which may prevent the loading of processor
and chipset registers, or affect the ability to debug from cold boot and low power transitions.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.