Datasheet

R
38 Specification Update
V2. BR0# Maximum Hold Time Specification Change
The BR0# maximum hold time has changed to 2 BCLKs. This change will be shown in the “System
Bus AC Specifications (Reset Conditions)” table and “System Bus Reset and Configuration Timings”
figure of the Mobile Intel
®
Celeron
®
Processor on .13 Micron Process in Micro-FCPGA Package
Datasheet. This change will be incorporated in the next revision of the datasheet.
Currently it states:
Table 21. System Bus AC Specifications (Reset Conditions)
T# Parameter Min Max Unit Figure Notes
T45: Reset Configuration Signals (A[31:3]#, BR0# INIT#, SMI#)
Setup Time
4 BCLKs 13 1
T46: Reset Configuration Signals (A[31:3]#, BR0# INIT#, SMI#)
Hold Time
2 20 BCLKs 13 2
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
It should state:
Table 21. System Bus AC Specifications (Reset Conditions)
T# Parameter Min Max Unit Figure Notes
T45: Reset Configuration Signals (A[31:3]#, BR0# INIT#,
SMI#) Setup Time
4 BCLKs 13 1
T46:Reset Configuration Signals (A[31:3]#,INIT#, SMI#)
Hold Time
2 20 BCLKs 13 2
T47: Reset Configuration Signal BR0# Hold Time 2 2 BCLKs 13 2
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.