User Manual

BIOS SETUP
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Featu res
DRA M Ti ming Sele ctable By SPD ITEM HEL P
CAS La tency Tim e 2.5 Menu Level
Active to Precharge Delay 7
DRAM RAS# to CAS# Delay 3
DRA M RAS# Prech arge 3
Me mor y Frequency Fo r Auto
System BIOS Cach eable En abled
Video BIOS Cacheable
Memory Hole At 15M-1 6M
Enabled
Disabled
AGP Aperture Size (MB) 128
** On-Chip VGA Setting **
On-Chip VGA
On-Chip Frame Bu ffer Size
Boot Display
Enabled
8MB
CRT
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is By SPD .
CAS Latency Time
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system
board designer should set the values in this field, depending on the
DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU. The
choices are 2 and 3.
Active to Precharge Delay
The default setting for the Active to Precharge Delay is 6 .
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to
accumulate its charge before the SDRAM refreshes. The default setting
for the Active to Precharge Delay is 3 .
38 2801550 User’s Manual