8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual
We Value Your Opinion Dear Intel Customer: We have updated the information that was provided in the 1992 version of the 8XC196MC User’s Manual, added information about the 8XC196MD and 8XC196MH, and corrected known errata. We hope these changes make it easier for you to use our products. Your feedback will help us to provide the information you need. We’ll use your responses to guide us in developing other manuals and new versions of this one.
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8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual August 2004 Order Number 272181-003
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CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3 1.2 1.3 RELATED DOCUMENTS .............................................................................................. 1-5 1.4 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-8 World Wide Web .....
8XC196MC, MD, MH USER’S MANUAL CHAPTER 3 PROGRAMMING CONSIDERATIONS 3.1 OVERVIEW OF THE INSTRUCTION SET.................................................................... 3-1 3.1.1 BIT Operands ............................................................................................................3-2 3.1.2 BYTE Operands ........................................................................................................3-2 3.1.3 SHORT-INTEGER Operands ...............................................
CONTENTS 4.1.5.1 Memory-mapped SFRs ........................................................................................4-5 4.1.5.2 Peripheral SFRs ...................................................................................................4-5 4.1.6 Register File ..............................................................................................................4-9 4.1.6.1 General-purpose Register RAM .........................................................................4-10 4.1.6.
8XC196MC, MD, MH USER’S MANUAL 5.6.6 Serial I/O Modes .....................................................................................................5-37 5.6.6.1 Synchronous SIO Transmit Mode Example .......................................................5-43 5.6.6.2 Synchronous SIO Receive Mode Example ........................................................5-47 5.6.6.3 Asynchronous SIO Transmit Mode Example .....................................................5-50 5.6.6.
CONTENTS 7.4.5 Determining Serial Port Status ................................................................................7-15 CHAPTER 8 FREQUENCY GENERATOR 8.1 FUNCTIONAL OVERVIEW............................................................................................ 8-1 8.2 PROGRAMMING THE FREQUENCY GENERATOR ................................................... 8-3 8.2.1 Configuring the Output ..............................................................................................8-3 8.2.
8XC196MC, MD, MH USER’S MANUAL 10.5.2 10.5.3 10.5.4 Reading the Current Value of the Down-counter ....................................................10-7 Enabling the PWM Outputs .....................................................................................10-8 Generating Analog Outputs ..................................................................................10-10 CHAPTER 11 EVENT PROCESSOR ARRAY (EPA) 11.1 EPA FUNCTIONAL OVERVIEW .........................................................
CONTENTS 12.6.1.4 Using Mixed Analog and Digital Inputs ............................................................12-13 12.6.2 Understanding A/D Conversion Errors ..................................................................12-13 CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS 13.1 MINIMUM CONNECTIONS ......................................................................................... 13-1 13.1.1 Unused Inputs ..........................................................................................
8XC196MC, MD, MH USER’S MANUAL 15.4 WAIT STATES (READY CONTROL)......................................................................... 15-17 15.5 BUS-CONTROL MODES........................................................................................... 15-21 15.5.1 Standard Bus-control Mode ..................................................................................15-22 15.5.2 Write Strobe Mode ................................................................................................
CONTENTS APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS B.1 SIGNAL NAME CHANGES........................................................................................... B-1 B.2 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. B-1 B.3 SIGNAL DESCRIPTIONS........................................................................................... B-12 B.4 DEFAULT CONDITIONS ..................................................................
8XC196MC, MD, MH USER’S MANUAL FIGURES Figure 2-1 2-2 2-3 2-4 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 6-1 6-2 6-3 6-4 6-5 7-1 7-2 7-3 7-4 xii Page 8XC196Mx Block Diagram ...........................................................................................2-3 Block Diagram of the Core ...........................................................................................2-3 Clock Circuitry ....
CONTENTS FIGURES Figure 7-5 7-6 7-7 7-8 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 12-1 12-2 Page Serial Port Frames in Mode 2 and 3.............................................................................7-9 Serial Port Control (SPx_CON) Register....................................................................7-10 Serial Port x Baud Rate (SPx_BAUD) Register........
8XC196MC, MD, MH USER’S MANUAL FIGURES Figure 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 14-1 14-2 14-3 14-4 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 xiv Page A/D Result (AD_RESULT) Register — Write Format .................................................12-6 A/D Time (AD_TIME) Register ...................................................................................
CONTENTS FIGURES Figure 15-21 15-22 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 Page 16-bit System with RAM ...........................................................................................15-31 System Bus Timing ..................................................................................................15-32 Unerasable PROM (USFR) Register..........................................................................
8XC196MC, MD, MH USER’S MANUAL TABLES Table 1-1 1-2 1-3 1-4 1-5 2-1 2-2 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-13 5-14 5-15 5-16 6-1 6-2 6-3 6-4 6-5 6-6 6-7 xvi Page Handbooks and Product Information ............................................................................1-6 Application Notes, Application Briefs, and Article Reprints ..........................................
CONTENTS TABLES Table 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 7-1 7-2 7-3 8-1 8-2 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 13-1 13-2 13-3 14-1 14-2 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 Page Control Register Values for Each Configuration.........................................................6-11 Port Configuration Example .......................................................................................
8XC196MC, MD, MH USER’S MANUAL TABLES Table 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 A-1 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 C-1 C-2 C-3 C-4 C-5 C-6 C-7 C-8 C-9 C-10 C-11 C-12 xviii Page 87C196Mx OTPROM Memory Map ..........................................................................16-3 Memory Protection for Normal Operating Mode.........................................................
1 Guide to This Manual
CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196MC, 8XC196MD, and 8XC196MH embedded microcontrollers. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you complete your design. 1.
8XC196MC, MD, MH USER’S MANUAL Chapter 9 — Waveform Generator — describes the waveform generator and explains how to configure it. For additional information and application examples, consult AP-483, Application Examples Using the 8XC196MC/MD Microcontroller (order number 272282). Chapter 10 — Pulse-width Modulator — provides a functional overview of the pulse width modulator (PWM) modules, describes how to program them, and provides sample circuitry for converting the PWM outputs to analog signals.
GUIDE TO THIS MANUAL Appendix C — Registers — provides a compilation of all device special-function registers (SFRs) arranged alphabetically by register mnemonic. It also includes tables that list the windowed direct addresses for all SFRs in each possible window. Glossary — defines terms with special meaning used throughout this manual. Index — lists key topics with page number references. 1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used throughout this manual.
8XC196MC, MD, MH USER’S MANUAL numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H. Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is appended to binary numbers for clarity.) register bits Bit locations are indexed by 7:0 (or 15:0), where bit 0 is the leastsignificant bit and bit 7 (or 15) is the most-significant bit.
GUIDE TO THIS MANUAL units of measure The following abbreviations are used to represent units of measure: A DCV Kbytes kHz kΩ mA Mbytes MHz ms mW ns pF W V µA µF µs µW X 1.3 amps, amperes direct current volts kilobytes kilohertz kilo-ohms milliamps, milliamperes megabytes megahertz milliseconds milliwatts nanoseconds picofarads watts volts microamps, microamperes microfarads microseconds microwatts Uppercase X (no italics) represents an unknown value or an irrelevant (“don’t care”) state or condition.
8XC196MC, MD, MH USER’S MANUAL Table 1-1. Handbooks and Product Information Title and Description Order Number Intel Embedded Quick Reference Guide Solutions for Embedded Applications Guide Data on Demand fact sheet Data on Demand annual subscription (6 issues; Windows* version) Complete set of Intel handbooks on CD-ROM. Handbook Set — handbooks and product overview Complete set of Intel’s product line handbooks.
GUIDE TO THIS MANUAL Table 1-2.
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GUIDE TO THIS MANUAL 1.4.4 World Wide Web We offer a variety of information through the World Wide Web (URL:http://www.intel.com/). Select “Embedded Design Products” from the Intel home page. 1.5 TECHNICAL SUPPORT In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S.
2 Architectural Overview
CHAPTER 2 ARCHITECTURAL OVERVIEW The 16-bit 8XC196MC, 8XC196MD, and 8XC196MH CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output (I/O) operations. They share a common architecture and instruction set with other members of the MCS® 96 microcontroller family. NOTE This manual describes a family of microcontrollers. For brevity, the name 8XC196Mx is used when the discussion applies to all family members.
8XC196MC, MD, MH USER’S MANUAL Table 2-1.
ARCHITECTURAL OVERVIEW Optional ROM Core Interrupt Controller Clock and Power Mgmt. I/O PWM EPA PTS WG A/D FG WDT SIO Note: The frequency generator is unique to the 8XC196MD. The serial I/O port is unique to the 8XC196MH. A2798-02 Figure 2-1. 8XC196Mx Block Diagram Memory Controller CPU Register File Register RAM RALU Prefetch Queue Microcode Engine Slave PC ALU Address Register Master PC Data Register PSW CPU SFRs Registers Bus Controller A2797-01 Figure 2-2.
8XC196MC, MD, MH USER’S MANUAL 2.3.1 CPU Control The CPU is controlled by the microcode engine, which instructs the RALU to perform operations using bytes, words, or double-words from either the 256-byte lower register file or through a window that directly accesses the upper register file. (See Chapter 4, “Memory Partitions,” for more information about the register file and windowing.) CPU instructions move from the 4-byte prefetch queue in the memory controller into the RALU’s instruction register.
ARCHITECTURAL OVERVIEW The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as temporary registers for many instructions. These registers have their own shift logic and are used for operations that require logical shifts, including normalize, multiply, and divide operations. The six-bit loop counter counts repetitive shifts.
8XC196MC, MD, MH USER’S MANUAL 2.3.4 Memory Interface Unit The RALU communicates with all memory, except the register file and peripheral SFRs, through the memory controller. (It communicates with the upper register file through the memory controller except when windowing is used; see Chapter 4, “Memory Partitions.”) The memory controller contains the prefetch queue, the slave program counter (slave PC), address and data registers, and the bus controller.
ARCHITECTURAL OVERVIEW 2.4 INTERNAL TIMING The clock circuitry (Figure 2-3) receives an input clock signal on XTAL1 provided by an external crystal or oscillator and divides the frequency by two. The clock generators accept the divided input frequency from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2. These signals are active when high. .
8XC196MC, MD, MH USER’S MANUAL XTAL1 TXTAL1 TXTAL1 1 State Time 1 State Time PH1 PH2 CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0114-04 Figure 2-4. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. Table 2-2.
ARCHITECTURAL OVERVIEW 2.5.1 I/O Ports The 8XC196Mx microcontrollers have seven I/O ports, ports 0–6. The 8XC196MD has an additional port, port 7. Individual port pins are multiplexed to serve as standard I/O or to carry specialfunction signals associated with an on-chip peripheral or an off-chip component. If a particular special-function signal is not used in an application, the associated pin can be individually configured to serve as a standard I/O pin.
8XC196MC, MD, MH USER’S MANUAL 2.5.3 Event Processor Array (EPA) and Timer/Counters The event processor array (EPA) performs high-speed input and output functions associated with its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an event occurs, the EPA records the timer value associated with it. This is a capture event. In the output mode, the EPA monitors a timer until its value matches that of a stored time value.
ARCHITECTURAL OVERVIEW 2.5.7 Analog-to-digital Converter The analog-to-digital (A/D) converter converts an analog input voltage to a digital equivalent. Resolution is either 8 or 10 bits; sample and convert times are programmable. Conversions can be performed on the analog ground and reference voltage, and the results can be used to calculate gain and zero-offset errors. The internal zero-offset compensation circuit enables automatic zerooffset adjustment.
8XC196MC, MD, MH USER’S MANUAL 2.6.3 Programming the Nonvolatile Memory MCS 96 microcontrollers that have internal OTPROM provide several programming options: • Slave programming allows a master EPROM programmer to program and verify one or more slave MCS 96 microcontrollers. Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer’s code and data.
3 Programming Considerations
CHAPTER 3 PROGRAMMING CONSIDERATIONS This section provides an overview of the instruction set of the MCS® 96 microcontrollers and offers guidelines for program development. For detailed information about specific instructions, see Appendix A. OVERVIEW OF THE INSTRUCTION SET 3.1 The instruction set supports a variety of operand types likely to be useful in control applications (see Table 3-1). NOTE The operand-type variables are shown in all capitals to avoid confusion.
8XC196MC, MD, MH USER’S MANUAL Table 3-2 lists the equivalent operand-type names for both C programming and assembly language. Table 3-2. Equivalent Operand Types for Assembly and C Programming Languages Operand Types Assembly Language Equivalent C Programming Language Equivalent BYTE BYTE unsigned char SHORT-INTEGER BYTE char WORD WORD unsigned int INTEGER WORD int DOUBLE-WORD LONG unsigned long LONG-INTEGER LONG long 3.1.
PROGRAMMING CONSIDERATIONS WORDs must be aligned at even byte boundaries in the address space. The least-significant byte of the WORD is in the even byte address, and the most-significant byte is in the next higher (odd) address. The address of a WORD is that of its least-significant byte (the even byte address). WORD operations to odd addresses are not guaranteed to operate in a consistent manner. 3.1.
8XC196MC, MD, MH USER’S MANUAL 3.1.7 LONG-INTEGER Operands A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648 (– 231) through +2,147,483,647 (+231–1). The architecture directly supports LONG-INTEGER operands only as the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations.
PROGRAMMING CONSIDERATIONS 3.2 ADDRESSING MODES The instruction set uses four basic addressing modes: • • • • direct immediate indirect (with or without autoincrement) indexed (short-, long-, or zero-indexed) The stack pointer can be used with indirect addressing to access the top of the stack, and it can also be used with short-indexed addressing to access data within the stack. The zero register can be used with long-indexed addressing to access any memory location.
8XC196MC, MD, MH USER’S MANUAL Table 3-3. Definition of Temporary Registers Temporary Register Description AX word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte BX word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte CX word-aligned 16-bit register; CH is the high byte of CX and CL is the low byte DX word-aligned 16-bit register; DH is the high byte of DX and DL is the low byte 3.2.
PROGRAMMING CONSIDERATIONS ; AL ← BL + MEM_BYTE(CX) ; MEM_WORD(AX) ← MEM_WORD(SP) ; SP ← SP + 2 ADDB AL,BL,[CX] POP [AX] 3.2.3.1 Indirect Addressing with Autoincrement You can choose to automatically increment the indirect address after the current access. You specify autoincrementing by adding a plus sign (+) to the end of the indirect reference.
8XC196MC, MD, MH USER’S MANUAL The instruction LD AX,12H[BX] loads AX with the contents of the memory location that resides at address BX+12H. That is, the instruction adds the constant 12H (the offset) to the contents of BX (the base address), then loads AX with the contents of the resulting address. For example, if BX contains 1000H, then AX is loaded with the contents of location 1012H.
PROGRAMMING CONSIDERATIONS 3.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS The assembly language simplifies the choice of addressing modes. Use these features wherever possible. 3.3.1 Direct Addressing The assembly language chooses between direct and zero-indexed addressing depending on the memory location of the operand. Simply refer to the operand by its symbolic name. If the operand is in the lower register file, the assembly language chooses a direct reference.
8XC196MC, MD, MH USER’S MANUAL To use these registers effectively, you must have some overall strategy for allocating them. The C programming language adopts a simple, effective strategy. It allocates the eight bytes beginning at address 1CH as temporary storage and treats the remaining area in the register file as a segment of memory that is allocated as required.
PROGRAMMING CONSIDERATIONS If a procedure returns a value to the calling code (as opposed to modifying more global variables), the result is returned in the temporary storage space (TMPREG0, in this example) starting at 1CH. TMPREG0 is viewed as either an 8-, 16-, or 32bit variable, depending on the type of the procedure.
8XC196MC, MD, MH USER’S MANUAL When using the watchdog timer (WDT) for software protection, we recommend that you reset the WDT from only one place in code, reducing the chance of an undesired WDT reset. The section of code that resets the WDT should monitor the other code sections for proper operation. This can be done by checking variables to make sure they are within reasonable values.
4 Memory Partitions
CHAPTER 4 MEMORY PARTITIONS This chapter describes the address space, its major partitions, and a windowing technique for accessing the upper register file and peripheral SFRs with register-direct instructions. 4.1 MEMORY PARTITIONS Table 4-1 is a memory map of the 8XC196Mx devices. The remainder of this section describes the partitions. 4.1.1 External Devices (Memory or I/O) Several partitions are assigned to external devices (see Table 4-1). Data can be stored in any part of this memory.
8XC196MC, MD, MH USER’S MANUAL Table 4-1. Memory Map Device and Hex Address Range Description Addressing Modes MC, MD MH FFFF 6000 FFFF A000 External device (memory or I/O) connected to the address/data bus Indirect or indexed 5FFF 2080 9FFF 2080 Program memory (internal nonvolatile or external memory); see Note 1.
MEMORY PARTITIONS 4.1.4 Special-purpose Memory Special-purpose memory resides in locations 2000–207FH (Table 4-2). It contains several reserved memory locations, the chip configuration bytes (CCBs), and vectors for both peripheral transaction server (PTS) and standard interrupts. Accesses to this address range are directed to internal memory if EA# is held high and to external memory if EA# is held low. For devices without internal nonvolatile memory, the EA# signal must be tied low.
8XC196MC, MD, MH USER’S MANUAL 4.1.4.3 Security Key The security key prevents unauthorized programming access to the nonvolatile memory. See Chapter 16, “Programming the Nonvolatile Memory,” for details. 4.1.4.4 Chip Configuration Bytes (CCBs) The chip configuration bytes (CCBs) specify the operating environment. They specify the bus width, bus-control mode, and wait states. They also control powerdown mode, the watchdog timer, and nonvolatile memory protection.
MEMORY PARTITIONS 4.1.5.1 Memory-mapped SFRs Locations 1FE0–1FFFH contain memory-mapped SFRs (see Table 4-3). Locations in this range that are omitted from the table are reserved. The memory-mapped SFRs must be accessed with indirect or indexed addressing modes, and they cannot be windowed. If you read a location in this range through a window, the SFR appears to contain FFH (all ones). If you write a location in this range through a window, the write operation has no effect on the SFR.
8XC196MC, MD, MH USER’S MANUAL Table 4-4.
MEMORY PARTITIONS Table 4-5.
8XC196MC, MD, MH USER’S MANUAL Table 4-6.
MEMORY PARTITIONS 4.1.6 Register File The register file (Figure 4-1) is divided into an upper register file and a lower register file. The upper register file consists of general-purpose register RAM. The lower register file contains general-purpose register RAM along with the stack pointer (SP) and the CPU special-function registers (SFRs). Table 4-1 on page 4-2 lists the register file memory addresses. The RALU accesses the lower register file directly, without the use of the memory controller.
8XC196MC, MD, MH USER’S MANUAL Table 4-7. Register File Memory Addresses Device and Hex Address Range Description Addressing Modes MC, MD MH 01FF 0100 02FF 0100 Upper register file (register RAM) Indirect, indexed, or windowed direct 00FF 001A 00FF 001A Lower register file (register RAM) Direct, indirect, or indexed 0019 0018 0019 0018 Lower register file (stack pointer) Direct, indirect, or indexed 0017 0000 0017 0000 Lower register file (CPU SFRs) Direct, indirect, or indexed 4.1.6.
MEMORY PARTITIONS Your program must load a word-aligned (even) address into the stack pointer. Select an address that is two bytes greater than the desired starting address because the CPU automatically decrements the stack pointer before it pushes the first byte of the return address onto the stack. Remember that the stack grows downward, so allow sufficient room for the maximum number of stack entries. The stack must be located in either the internal register file or external RAM.
8XC196MC, MD, MH USER’S MANUAL 4.2 WINDOWING Windowing expands the amount of memory that is accessible with register-direct addressing. Register-direct addressing can access the lower register file with short, fast-executing instructions. With windowing, register-direct addressing can also access the upper register file and peripheral SFRs. Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into the lower register file.
MEMORY PARTITIONS 4.2.1 Selecting a Window The window selection register (Figure 4-3) selects a window to be mapped into the top of the lower register file. Table 4-9 provides a quick reference of WSR values for windowing the peripheral SFRs. Table 4-10 on page 4-14 lists the WSR values for windowing the upper register file. Address: Reset State: WSR 0014H 00H The window selection register (WSR) maps sections of RAM into the top of the lower register file, in 32-, 64-, or 128-byte increments.
8XC196MC, MD, MH USER’S MANUAL Table 4-10.
MEMORY PARTITIONS Table 4-11.
8XC196MC, MD, MH USER’S MANUAL Appendix C includes a table of the windowable SFRs with the WSR values and direct addresses for each window size. The following examples explain how to determine the WSR value and direct address for any windowable location. An additional example shows how to set up a window by using the linker locator. 4.2.2.
MEMORY PARTITIONS 4.2.2.5 Using the Linker Locator to Set Up a Window In this example, the linker locator is used to set up a window. The linker locator locates the window in the upper register file and determines the value to load in the WSR for access to that window. (Please consult the manual provided with the linker locator for details.
8XC196MC, MD, MH USER’S MANUAL ldb wsr, #?WSR ;Prolog code for wsr add var1, var2, var3 ; ; ; ldb wsr, [sp] add sp, #2 ret ;Epilog code for wsr ;Epilog code for wsr end ****************************** The following is an example of a linker invocation to link and locate the modules and to determine the proper windowing. RL196 MOD1.OBJ, MOD2.OBJ registers(100h-01ffh) windowsize(32) The above linker controls tell the linker to use registers 0100–01FFH for windowing and to use a window size of 32 bytes.
MEMORY PARTITIONS The C compiler can also take advantage of this feature if the “windows” switch is enabled. For details, see the MCS 96 microcontroller architecture software products in the Development Tools Handbook. 4.2.3 Windowing and Addressing Modes Once windowing is enabled, the windowed locations can be accessed both through the window using direct (8-bit) addressing and by the usual 16-bit addressing.
5 Standard and PTS Interrupts
CHAPTER 5 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It discusses the three special interrupts and the seven PTS modes, four of which are used with the EPA to provide a software serial I/O channel for both synchronous and asynchronous transfers and receptions. It also explains interrupt programming and control. 5.
8XC196MC, MD, MH USER’S MANUAL Interrupt Pending or PTSSRV Bit Set NMI Pending ? Yes No No INT_MASK.x = 1? Return Yes PTS Enabled? No Yes PTSSEL.x Bit = 1? Priority Encoder Highest Priority Interrupt Priority Encoder Yes Highest Priority PTS Interrupt Reset INT_PEND.x Bit Execute 1 PTS Cycle (Microcoded) Decrement PTSCOUNT No Return No Yes Return No Interrupts Enabled ? Yes PTSCOUNT = 0? Yes Clear PTSSEL.x Bit Set PTSSRV.x Bit PTSSRV.x = 1? Reset PTSSRV.x Bit No Reset INT_PEND.
STANDARD AND PTS INTERRUPTS Figure 5-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” represents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both the INT_PEND and INT_PEND1 registers. 5.2 INTERRUPT SIGNALS AND REGISTERS Table 5-1 describes the external interrupt signals and Table 5-2 describes the control and status registers for both the interrupt controller and PTS. Table 5-1.
8XC196MC, MD, MH USER’S MANUAL Table 5-2. Interrupt and PTS Control and Status Registers (Continued) Mnemonic PI_PEND Address 1FBEH Description Peripheral Interrupt Pending Any bit set indicates a pending interrupt request. PSW No direct access Processor Status Word This register contains one bit that globally enables or disables servicing of all maskable interrupts and another that enables or disables the PTS.
STANDARD AND PTS INTERRUPTS Table 5-3.
8XC196MC, MD, MH USER’S MANUAL 5.3.1 Special Interrupts This microcontroller has three special interrupt sources that are always enabled: unimplemented opcode, software trap, and NMI. These interrupts are not affected by the EI (enable interrupts) and DI (disable interrupts) instructions, and they cannot be masked. All of these interrupts are serviced by the interrupt controller; they cannot be assigned to the PTS. Of these three, only NMI goes through the transition detector and priority encoder.
STANDARD AND PTS INTERRUPTS When the level-sensitive event is selected, the external interrupt signal must remain asserted for at least 24 TXTAL1 (24/FXTAL1) to be recognized as a valid interrupt. When the signal is asserted, the level sampler samples the level of the signal three times during a 24 TXTAL1 period. When a valid level occurs, the level sampler generates a a single output pulse. The output pulse generates the EXTINT interrupt request.
8XC196MC, MD, MH USER’S MANUAL The interrupt service routine should read the PI_PEND (Figure 5-12 on page 5-23) register to determine the source of the interrupt. Before executing the return instruction, the interrupt service routine should check to see if any of the other interrupt sources are pending. Generally, PTS interrupt service is not useful for multiplexed interrupts because the PTS cannot readily determine the interrupt source.
STANDARD AND PTS INTERRUPTS 5.3.4 End-of-PTS Interrupts When the PTSCOUNT register decrements to zero at the end of a single transfer, block transfer, A/D scan, or serial I/O routine, hardware clears the corresponding bit in the PTSSEL register, (Figure 5-6 on page 5-14) which disables PTS service for that interrupt. It also sets the corresponding PTSSRV bit, requesting an end-of-PTS interrupt. An end-of-PTS interrupt has the same priority as a corresponding standard interrupt.
8XC196MC, MD, MH USER’S MANUAL Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS response to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer of an entire block of bytes or words. This means a worst-case latency of 500 states if you assume a block transfer of 32 words from one external memory location to another. See Table 5-4 on page 5-12 for PTS cycle execution times. 5.4.
STANDARD AND PTS INTERRUPTS 39 4 3 2 1 Execution Ending Instruction End "NORML" "NORML" 11 2 Call is Forced If Stack External 12 "PUSHA" Interrupt Routine EXTINT Pending Interrupt 6 If Stack External Set Cleared 56 State Times Response Time A0136-02 Figure 5-4. Standard Interrupt Response Time 5.4.2.2 PTS Interrupt Latency The maximum delay for a PTS interrupt is 43 state times (4 + 39) as shown in Figure 5-5.
8XC196MC, MD, MH USER’S MANUAL Table 5-4.
STANDARD AND PTS INTERRUPTS When you assign an interrupt to the PTS, you must set up a PTS control block (PTSCB) for each interrupt source (see “Initializing the PTS Control Blocks” on page 5-24) and use the EPTS instruction to globally enable the PTS. When you assign an interrupt to a standard software service routine, use the EI (enable interrupts) instruction to globally enable interrupt servicing. NOTE The DI (disable interrupts) instruction does not disable PTS service.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: PTSSEL 0004H 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
STANDARD AND PTS INTERRUPTS Address: Reset State: INT_MASK 0008H 00H The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register. Interrupt calls cannot occur immediately following this instruction. POPF or POPA restores it.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: INT_MASK1 0013H 00H The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
STANDARD AND PTS INTERRUPTS Address: Reset State: PI_MASK 1FBCH AAH The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM).
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: PI_MASK (Continued) 1FBCH AAH The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM).
STANDARD AND PTS INTERRUPTS Note that location 2002H in the interrupt vector table must be loaded with the value of the label AD_DONE_ISR before the interrupt request occurs and that the A/D conversion complete interrupt must be enabled for this routine to execute. This routine, like all interrupt service routines, is handled in the following manner: 1. After the hardware detects and prioritizes an interrupt request, it generates and executes an interrupt call.
8XC196MC, MD, MH USER’S MANUAL 5.5.2 Determining the Source of an Interrupt When hardware detects an interrupt, it sets the corresponding bit in the INT_PEND or INT_PEND1 register (Figures 5-10 and 5-11 ). It sets the bit even if the individual interrupt is disabled (masked). Hardware clears the pending bit when the program vectors to the interrupt service routine. The interrupt service routine can read INT_PEND and INT_PEND1 to determine which interrupts are pending.
STANDARD AND PTS INTERRUPTS Address: Reset State: INT_PEND 0009H 00H When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: INT_PEND1 0012H 00H When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
STANDARD AND PTS INTERRUPTS Address: Reset State: PI_PEND 1FBEH AAH When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by setting a PI_PEND bit.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: PI_PEND (Continued) 1FBEH AAH When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by setting a PI_PEND bit.
STANDARD AND PTS INTERRUPTS The address of the first (lowest) PTSCB byte is stored in the PTS vector table in special-purpose memory (see “Special-purpose Memory” on page 4-3). Figure 5-13 shows the PTSCB for each PTS mode. Unused PTSCB bytes can be used as extra RAM. NOTE The PTSCB must be located in the internal register file. The location of the first byte of the PTSCB must be aligned on a quad-word boundary (an address evenly divisible by 8).
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: PTSSRV 0006H 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
STANDARD AND PTS INTERRUPTS 5.6.2 Selecting the PTS Mode The second byte of each PTSCB is always an 8-bit value called PTSCON. Bits 5–7 select the PTS mode (Figure 5-15). The function of bits 0–4 differ for each PTS mode. Refer to the sections that describe each mode in detail to see the function of these bits. Table 5-4 on page 5-12 lists the cycle execution times for each PTS mode.
8XC196MC, MD, MH USER’S MANUAL PTS Single Transfer Mode Control Block In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).
STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block (Continued) Register PTSCON Location PTSCB + 1 Function PTS Control Bits M2:0 PTS Mode M2 1 BW M1 0 M0 0 single transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer SU† Update PTSSRC 0 = reload original PTS source address after each byte or word transfer 1 = retain current PTS source address after each byte or word transfer DU† Update PTSDST 0 = reload original PTS destination address after each byte or word tran
8XC196MC, MD, MH USER’S MANUAL Table 5-5. Single Transfer Mode PTSCB Unused Unused PTSDST (H) = 60H PTSDST (L) = 00H PTSSRC (H) = 00H PTSSRC (L) = 20H PTSCON = 85H (Mode = 100, BW = 0, SI/SU = 0, DI/DU = 1) PTSCOUNT = 09H 5.6.4 Block Transfer Mode In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from one memory location to another. See AP-483, Application Examples Using the 8XC196MC/MD Microcontroller, for application examples with code.
STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).
8XC196MC, MD, MH USER’S MANUAL PTS Block Transfer Mode Control Block (Continued) Register PTSCON Location PTSCB + 1 Function PTS Control Bits M2:0 PTS Mode These bits select the PTS mode: M2 0 BW M1 0 M0 0 block transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer SU Update PTSSRC 0 = reload original PTS source address after each block transfer is complete 1 = retain current PTS source address after each block transfer is complete DU Update PTSDST 0 = reload original PTS destina
STANDARD AND PTS INTERRUPTS PTS A/D Scan Mode Control Block In A/D scan mode, the PTS causes the A/D converter to perform multiple conversions on one or more channels and then stores the results. The control block contains pointers to both the AD_RESULT register (PTSPTR1) and a table of A/D conversion commands and results (PTSPTR2), a control register (PTSCON), and an A/D conversion count (PTSCOUNT).
8XC196MC, MD, MH USER’S MANUAL PTS A/D Scan Mode Control Block (Continued) PTSCOUNT PTSCB + 0 Consecutive A/D Conversions Defines the number of A/D conversions that will be completed during the A/D scan routine. Each cycle consists of the PTS transferring the A/D conversion results into the command/data table, and then loading a new command into the AD_COMMAND register. Maximum number is 255. Figure 5-18.
STANDARD AND PTS INTERRUPTS 5.6.5.1 A/D Scan Mode Cycles Software must start the first A/D conversion. After the A/D conversion complete interrupt initiates the PTS routine, the following actions occur. 1. The PTS reads the first command (from address XXXX), stores it in a temporary location, and increments the PTSPTR1 register twice. PTSPTR1 now points to the first blank location in the command/data table (address XXXX + 2). 2.
8XC196MC, MD, MH USER’S MANUAL version. Step 4 updates PTSPTR1 (PTSPTR1 now points to 3004H) and step 5 decrements PTSCOUNT to 3. The next cycle begins by storing the channel 5 command in the temporary location. During the last cycle (PTSCOUNT = 1), the dummy command is loaded into the AD_COMMAND register and no conversion is performed. PTSCOUNT is decremented to zero and the end-of-PTS interrupt is requested. Table 5-8.
STANDARD AND PTS INTERRUPTS 5.6.5.3 A/D Scan Mode Example 2 Table 5-11 sets up a series of ten PTS cycles, each of which reads a single A/D channel and stores the result in a single location (3002H). The UPDT bit (PTSCON.3) is cleared so that original contents of PTSPTR1 are restored after the cycle. The command/data table is shown in Table 5-10. Table 5-10. Command/Data Table (Example 2) Address Contents 3002H AD_RESULT for ACHx 3000H Unused AD_COMMAND for ACHx Table 5-11.
8XC196MC, MD, MH USER’S MANUAL transmitted or received including the parity and stop bits in the asynchronous modes. The serial I/O modes require two PTS control blocks to configure all options (see Figures 5-19 and 5-20). These blocks need not be contiguous, but they must each be located in register RAM on a quadword boundary. See AP-483, Application Examples Using the 8XC196MC/MD Microcontroller, for application examples with code.
STANDARD AND PTS INTERRUPTS PTS Serial I/O Mode Control Block 1 (Continued) (8XC196MC, MD) Register BAUD Location PTSCB1 + 4 Function Baud Value This register contains the 16-bit value that the PTS uses to generate the desired baud rate. Use the following formula to calculate the value to load into the BAUD register.
8XC196MC, MD, MH USER’S MANUAL PTS Serial I/O Mode Control Block 1 (Continued) (8XC196MC, MD) Register PTSCOUNT Location PTSCB1 + 0 Function Consecutive PTS Cycles Defines the number of bits to be transmitted or received, including parity and stop bits, but not the start bit. For asynchronous modes, program a number that is between 1–16. For synchronous modes, program a number that is twice the number of bits to be transmitted or received (2–32). PTSCOUNT is decremented at the end of each PTS cycle.
STANDARD AND PTS INTERRUPTS PTS Serial I/O Mode Control Block 2 (8XC196MC, MD) The PTS control block 2 contains pointers to both the port register (PORTREG) and the data register (DATA). It also contains a 16-bit value that is used to calculate the sample time for asynchronous receptions when majority sampling is selected (SAMPTIME), a control register (PTSCON1), and a 16bit value that is used to select the port signal that functions as the TXD or RXD signal (PORTMASK).
8XC196MC, MD, MH USER’S MANUAL PTS Serial I/O Mode Control Block 2 (Continued) (8XC196MC, MD) Register DATA Location PTSCB2 + 4 Function Data Register This 16-bit register holds the data to be transmitted or the data that has been received. During transmit mode, the leastsignificant bit (bit 0) is transmitted first. Data shifts to the right with each successive transmission. During receive mode, the first bit is loaded into the most-significant bit (bit 15).
STANDARD AND PTS INTERRUPTS PTS Serial I/O Mode Control Block 2 (Continued) (8XC196MC, MD) Register PORTMASK Location Function PTSCB2 + 2 Port Mask Register Select the port signal that will function as the transmit data (TXD) or receive data (RXD) signal by setting the corresponding bit. Clear all other bits to mask those signals. PORTREG PTSCB2 + 0 Port Address Pointer This 16-bit register contains the address of the port that will be used to transmit or receive data. Figure 5-20.
8XC196MC, MD, MH USER’S MANUAL If the SCK signal is generated by the EPA channel, the first PTS cycle must be started manually. • Initialize the TXD port pin and the SCK signal to the system-required logic level before starting a transmission. • Add the contents of the timer register to the Baud_value (Figure 5-19 on page 5-38) and store the result into the EPA time register. This sets up the timing for the first interrupt and causes the first bit transmission to occur at the proper baud rate.
STANDARD AND PTS INTERRUPTS Table 5-13. SSIO Transmit Mode PTSCBs 7. PTSCB1 PTSCB2 PTSVEC (H) = pointer to PTSCB2 Unused PTSVEC (L) = pointer to PTSCB2 SAMPTIME = unused BAUD (H) = 00H (9600 baud at 16 MHz) DATA (H) = unused BAUD (L) = D0H (9600 baud at 16 MHz) DATA (L) = nnH (8 data bits) EPAREG (H) = 1FH (EPA0_TIME) PTSCON1 = 02H (transmit data on odd PTS cycles) EPAREG (L) = 42H (EPA0_TIME) PORTMASK = 04H (P2.
8XC196MC, MD, MH USER’S MANUAL time into the event-time register. If this toggle occurs, the clock polarity will change because of the odd number of toggles and erroneous data may be output. The interrupt service routine should also load the next data byte, reload the PTSCOUNT and PTSCON1 registers, select PTS service for EPA0, reload both the EPA0_CONTROL and EPA0_TIME registers. 14. To determine when all bytes have been transmitted, create a loop routine to check the status of the TXDDONE flag.
STANDARD AND PTS INTERRUPTS 5.6.6.2 Synchronous SIO Receive Mode Example In synchronous serial I/O (SSIO) receive mode, an EPA channel controls the reception baud rate by generating or capturing a serial clock signal (SCK). To generate the SCK signal, configure the EPA channel in compare mode and set the output-pin toggle option. Whenever a match occurs between the EPA event-time register and a timer register, the EPA channel toggles SCK and generates an interrupt.
8XC196MC, MD, MH USER’S MANUAL The following example uses EPA0 to capture the SCK signal and P2.3 to receive the data (RXD). It sets up a synchronous serial I/O PTS routine that receives 16 bytes with eight data bits. Because this example uses an external serial clock input, the TIMER1 and BAUD registers are not used. The external clock source controls the baud rate. This example uses several user-defined registers.
STANDARD AND PTS INTERRUPTS 8. Select PTS service for EPA0. — Set PTSSEL.2. 9. Set-up EPA0 to capture on both rising and falling edges. — Set EPA0_CON bits 4 and 5 (Figure 11-10 on page 11-19). 10. Enable the PTS and conventional interrupts. — Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS. 11. Toggle the SCK input to start the reception.
8XC196MC, MD, MH USER’S MANUAL End-Of-PTS Interrupt Save Critical Data Disable EPA Channel Clear Interrupt Request Bit Save Received Data R_COUNT = R_COUNT - 1 R_COUNT = 0? Y N Set-up next data reception - Clear DATA register - Reload PTSCOUNT and PTSCON1 registers - Select PTS service for EPA channel - Re-initialize the EPA channel RXDDONE = 1 Load Critical Data Return A3275-01 Figure 5-24. Synchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart 5.6.6.
STANDARD AND PTS INTERRUPTS End-of-PTS Conventional Interrupt 10 PTS Serviced Interrupts Interrupts Software Clears TXD TXD (Port pin) Start LSB Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 1 Bit Time Parity Stop Optional Parity Bit A3119-01 Figure 5-25. Asynchronous SIO Transmit Timing The first PTS cycle must be started manually by generating a start bit and then setting up the timing for the first EPA interrupt. • Initialize the TXD port pin to one before starting a transmission.
8XC196MC, MD, MH USER’S MANUAL 5. Initialize and enable the timer; select up counting, internal clock, and prescaler disabled. — Set T1CONTROL bits 6 and 7 (Figure 11-8 on page 11-16). 6. Initialize the PTSCB as shown in Table 5-15. Table 5-15.
STANDARD AND PTS INTERRUPTS 14. The transmission will begin. Data is shifted out with the least-significant (rightmost) bit first. Each time a timer match occurs between EPA0_TIME and TIMER1, the EPA0 channel generates an interrupt and the PTS outputs the next bit of data on the pin configured as TXD. When PTSCOUNT decrements to zero, the PTS calls the end-of-PTS interrupt (Figure 5-26).
8XC196MC, MD, MH USER’S MANUAL End-Of-PTS Interrupt Save Critical Data Is PTS Cycle Completed? N Y Disable EPA Channel Clear Interrupt Request Bit T_COUNT = T_COUNT - 1 T_COUNT = 0? Y N Set-up next data transfer - Load next data byte into DATA register - Reload PTSCOUNT and PTSCON1 registers - Create start bit (clear TXD) - Select PTS service for EPA channel - Re-initialize the EPA channel - Re-initialize the EPA timer to initiate first bit transfer TXDDONE = 1 Load Critical Data Return A3276
STANDARD AND PTS INTERRUPTS 5.6.6.4 Asynchronous SIO Receive Mode Example In asynchronous serial I/O (ASIO) receive mode, an EPA channel is set up to capture the falling edge when the data start bit toggles on a port pin that is configured to function as the Receive Data signal (RXD). When the capture occurs, the EPA generates a conventional interrupt which starts the asynchronous receive process. This conventional interrupt service routine would be the same as the end-of-PTS interrupt service routine.
8XC196MC, MD, MH USER’S MANUAL 2. Set-up the stack pointer. 3. Reset all interrupt mask registers. — Clear INT_MASK, INT_MASK1and PI_MASK. 4. Initialize P2.0 to function as the RXD signal. — Set P2_DIR.0 (selects input). — Clear P2_MODE.0 (selects LSIO function). — Set P2_REG.0 (initializes RXD input to “1”). 5. Initialize and enable the timer; select up counting, internal clock, and prescaler disabled. — Set T1CONTROL bits 6 and 7 (Figure 11-8 on page 11-16). 6.
STANDARD AND PTS INTERRUPTS 11. Enable the PTS and conventional interrupts. — Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS. 12. Toggle the RXD input to start the reception. The EPA will generate a conventional interrupt. This interrupt service routine should be the same as the end-of-PTS rountine. The service routine can determine if this is a start reception interrupt or a end-of-PTS interrupt by reading the EPA0_CON register.
8XC196MC, MD, MH USER’S MANUAL End-Of-PTS Interrupt Save Critical Data Y Start Bit? N Disable EPA Channel Clear Interrupt Request Bit Y Start Bit Error? Y Framing Error? N N Initialize EPA Channel Parity Error? Set Time To First Bit Sample Save Received Data Y N RXDDONE = 3 R_COUNT = R_COUNT - 1 Enable PTS Service for EPA Channel R_COUNT = 0? Y N Set-up next data reception - Clear DATA register - Reload PTSCOUNT and PTSCON1 registers - Select PTS service for EPA channel - Re-initialize
6 I/O Ports
CHAPTER 6 I/O PORTS I/O ports provide a mechanism to transfer information between the device and the surrounding system circuitry. They can read system status, monitor system operation, output device status, configure system options, generate control signals, provide serial communication, and so on. Their usefulness in an application is limited only by the number of I/O pins available and the imagination of the engineer. 6.
8XC196MC, MD, MH USER’S MANUAL 6.2 INPUT-ONLY PORTS 1 (MC, MD ONLY) AND 0 Port 0 is an eight-bit, high-impedance, input-only port that provides analog and digital inputs. The input-only pins can be read as digital inputs; most of them are also inputs to the A/D converter. The input-only ports differ from the other standard ports in that their pins can be used only as inputs to the digital or analog circuitry.
I/O PORTS Table 6-3. Input-only Port Registers Mnemonic Address Description P0_PIN 1FA8H (MC, MD) 1FDAH (MH) Each bit of P0_PIN reflects the current state of the corresponding port 0 pin. P1_PIN (MC, MD) 1FA9H (MC, MD) Each bit of P1_PIN reflects the current state of the corresponding port 1 pin. 6.2.1 Standard Input-only Port Operation Figure 6-1 is a schematic of an input-only port pin.
8XC196MC, MD, MH USER’S MANUAL 6.2.2 Standard Input-only Port Considerations Port 0 and 1 pins are unique in that they may individually be used as digital inputs and analog inputs at the same time. However, reading the port induces noise into the A/D converter, decreasing the accuracy of any conversion in progress. We strongly recommend that you not read the port while an A/D conversion is in progress. To reduce noise, the P0_PIN or P1_PIN register is clocked only when the port is read.
I/O PORTS Table 6-4. Bidirectional Port Pins Port Pin Special-function Signal(s) Special-function Signal Type Associated Peripheral P1.0 (MH) TXD0 O SIO P1.1 (MH) RXD0 I/O SIO P1.2 (MH) TXD1 O SIO P1.3 (MH) RXD1 I/O SIO P2.0 EPA0 I/O EPA EPA1 (MC, MD) I/O EPA SCLK0# (MH) BCLK0 (MH) I/O I SIO SIO EPA2 (MC, MD) I/O EPA EPA1 (MH) I/O EPA EPA3 (MC, MD) I/O EPA COMP3 (MH) O EPA P2.4 COMP0 O EPA P2.5 COMP1 O EPA P2.6 COMP2 O EPA COMP3 (MC, MD) O EPA P2.
8XC196MC, MD, MH USER’S MANUAL Table 6-5 lists the registers associated with the bidirectional ports. Each port has three control registers (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN register is a status register that returns the logic level present on the pins; it can only be read. The registers for the standard ports are byte-addressable and can be windowed. The port 5 registers must be accessed using 16-bit addressing and cannot be windowed.
I/O PORTS In I/O mode (selected by clearing Px_MODE.y), Px_REG and Px_DIR are input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high impedance. Table 6-6 is a logic table for I/O operation of these ports. In special-function mode (selected by setting Px_MODE.y), SFDIR and SFDATA are input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high impedance.
8XC196MC, MD, MH USER’S MANUAL Internal Bus Vcc Px_REG 0 SFDATA Q1 1 I/O Pin Px_DIR 0 Q2 SFDIR 1 Vss Px_MODE Sample Latch 150Ω to 200Ω R1 Px_PIN Q D LE Read Port PH1 Clock Vcc Medium Pullup 300ns Delay Q3 RESET# Vcc RESET# Weak Pullup R Q Any Write to Px_MODE Q4 S A0238-04 Figure 6-2.
I/O PORTS Table 6-6. Logic Table for Bidirectional Ports in I/O Mode Configuration Open-drain Output Complementary Output Input Px_MODE 0 0 0 0 Px_DIR 0 0 1 1 SFDIR X X X X SFDATA X X X X Px_REG 0 1 0, 1 (Note 2) 1 Q1 off on off off Q2 on off on, off (Note 2) off Px_PIN 0 1 X (Note 3) high impedance (Note 4) NOTES: 1. X = Don’t care. 2. If Px_REG is cleared, Q2 is on; if Px_REG is set, Q2 is off. 3. Px_PIN contains the current value on the pin. 4.
8XC196MC, MD, MH USER’S MANUAL To prevent the CMOS inputs from floating, the bidirectional port pins are weakly pulled high during and after reset, until your software writes to Px_MODE. The default values of the control registers after reset configure the pins as high-impedance inputs with weak pull-ups. To ensure that the ports are initialized correctly and that the weak pull-ups are turned off, follow this suggested initialization sequence: 1.
I/O PORTS Table 6-8.
8XC196MC, MD, MH USER’S MANUAL Table 6-10. Port Pin States After Reset and After Example Code Execution Resulting Pin States† Action or Code Reset LDB Px_DIR, #00011111B Px.7 Px.6 Px.5 Px.4 Px.3 Px.2 Px.1 Px.0 wk1 wk1 wk1 wk1 wk1 wk1 wk1 wk1 1 1 1 wk1 wk1 wk1 wk1 wk1 LDB Px_MODE, #00000000B 1 1 1 HZ1 HZ1 HZ1 HZ1 HZ1 LDB Px_REG, #10010011B 1 0 0 HZ1 0 0 HZ1 HZ1 † wk1 = weakly pulled high, HZ1 = high impedance (actually a “1” with an external pull-up). 6.3.
I/O PORTS P5.0/ALE If EA# is high on reset (internal access), the pin is weakly held high until your software writes to P5_MODE. If EA# is low on reset (external access), either ALE or ADV# is activated as a system control pin, depending on the ALE bit of CCR0. In either case, the pin becomes a true complementary output. P5.1/INST This pin remains weakly held high until your software writes configuration data into P5_MODE. P5.
8XC196MC, MD, MH USER’S MANUAL 6.4 BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS) Ports 3 and 4 are eight-bit, bidirectional, memory-mapped I/O ports. They can be addressed only with indirect or indexed addressing and cannot be windowed. Ports 3 and 4 provide the multiplexed address/data bus. In programming modes, ports 3 and 4 serve as the programming bus (PBUS). Port 5 supplies the bus-control signals.
I/O PORTS 6.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation Figure 6-3 shows the ports 3 and 4 logic. During reset, the active-low level of RESET# turns off Q1 and Q2 and turns on transistor Q3, which weakly pulls the pin high. (Q1 can source at least – 3 mA at VCC –0.7 volts; Q2 can sink at least 3 mA at 0.45 volts; and Q3 can source approximately –10 µΑ at VCC –1.0 volts. Consult the datasheet for exact specifications.
8XC196MC, MD, MH USER’S MANUAL Table 6-13. Logic Table for Ports 3 and 4 as Open-drain I/O Configuration 6.4.2 Open-drain Px_REG 0 Q1 off off Q2 on off Px_PIN 0 high impedance 1 Using Ports 3 and 4 as I/O To use a port pin as an output, write the output data to the corresponding Px_REG bit. When the device requires access to external memory, it takes control of the port and drives the address/data bit onto the pin. The address/data bit replaces your output during this time.
I/O PORTS Table 6-14. Standard Output-only Port Pins Port Pin Special-function Signal(s) Special-function Signal Type Output Associated Peripheral P6.0 WG1# Waveform generator P6.1 WG1 Output Waveform generator P6.2 WG2# Output Waveform generator P6.3 WG2 Output Waveform generator P6.4 WG3# Output Waveform generator P6.5 WG3 Output Waveform generator P6.6 PWM0 Output PWM P6.7 PWM1 Output PWM Table 6-15.
8XC196MC, MD, MH USER’S MANUAL Internal Bus Vcc WG_OUTPUT Q1 Output Pin Combinational Logic Q2 A2764-01 Figure 6-4. Output-only Port Address: Reset State: WG_OUTPUT (Port 6) 1FC0H 0000H The port 6 output configuration (WG_OUTPUT) register controls port 6 functions. If you are using port 6 for general-purpose outputs, write C0H (for active-high outputs) or 00H (for active-low outputs) to the high byte of WG_OUTPUT, and write the desired pin values to the low byte.
I/O PORTS Address: Reset State: WG_OUTPUT (Port 6) (Continued) 1FC0H 0000H The port 6 output configuration (WG_OUTPUT) register controls port 6 functions. If you are using port 6 for general-purpose outputs, write C0H (for active-high outputs) or 00H (for active-low outputs) to the high byte of WG_OUTPUT, and write the desired pin values to the low byte.
7 Serial I/O (SIO) Port
CHAPTER 7 SERIAL I/O (SIO) PORT A serial input/output (SIO) port provides a means for the system to communicate with external devices. The 8XC196MH device has a two-channel serial I/O port that shares pins with ports 1 and 2. (The 8XC196MC and 8XC196MD devices do not have serial I/O ports.) This chapter describes the SIO port and explains how to configure it. Chapter 6, “I/O Ports,” explains how to configure the port pins for their special functions.
8XC196MC, MD, MH USER’S MANUAL An independent, 15-bit baud-rate generator controls the baud rate of the serial port. Either XTAL1 or BCLKx can provide the clock signal for modes 0–3. In mode 4, the internal shift clock is output on SCLKx# or an external shift clock is input on SCLKx# (in which case the baud-rate generator is not used). The baud-rate register (SPx_BAUD) selects the clock source and the baud rate.
SERIAL I/O (SIO) PORT Table 7-2. Serial Port Control and Status Registers (Continued) Mnemonic INT_PEND1 Address 0012H Description Interrupt Pending 1 When set, the TIx bit indicates a pending transmit interrupt. When set, the RIx bit indicates a pending receive interrupt. When set, the SPE bit indicates a pending serial port receive error interrupt. You must read the PI_PEND register to determine which channel generated the interrupt.
8XC196MC, MD, MH USER’S MANUAL Table 7-2. Serial Port Control and Status Registers (Continued) Mnemonic PI_MASK Address 1FBCH Description Peripheral Interrupt Mask This register enables and disables multiplexed peripheral interrupts. Setting an SPx bit enables a serial port receive error interrupt; clearing the bit disables (masks) the interrupt. PI_PEND 1FBEH Peripheral Interrupt Pending This register indicates pending multiplexed peripheral interrupts.
SERIAL I/O (SIO) PORT 7.3.1 Synchronous Modes (Modes 0 and 4) The 8XC196MH serial port has two synchronous modes, mode 0 and mode 4. Mode 0 is the synchronous mode available on all the 8XC196 devices that have serial ports. Mode 4 is an enhanced, full-duplex synchronous mode. 7.3.1.1 Mode 0 The most common use of mode 0 is to expand the I/O capability of the device with shift registers (see Figure 7-2).
8XC196MC, MD, MH USER’S MANUAL During a reception, the RI flag in SPx_STATUS is set after the stop bit is sampled. The RIx pending bit in the interrupt pending register is set immediately before the RI flag is set. During a transmission, the TI flag is set immediately after the end of the last (eighth) data bit is transmitted. The TIx pending bit in the interrupt pending register is generated when the TI flag in SPx_STATUS is set.
SERIAL I/O (SIO) PORT In mode 4, writing to SBUFx_TX starts a transmission regardless of whether RXDx is enabled. However, RXDx must be enabled to allow a reception. If RXDx is enabled, either a rising edge on the RXDx input or clearing the receive interrupt (RI) flag starts a reception. Disabling RXDx stops a reception in progress and inhibits further receptions. To avoid a partial or undesired complete reception, disable RXDx before clearing the RI flag.
8XC196MC, MD, MH USER’S MANUAL Stop Start D0 D1 D2 D3 D4 D5 D6 D7 Stop 8 Bits of Data or 7 Bits of Data with Parity Bit 10-bit Frame A0245-02 Figure 7-4. Serial Port Frames for Mode 1 The transmit and receive functions are controlled by separate shift clocks. The transmit shift clock starts when the baud-rate generator is initialized. The receive shift clock is reset when a start bit (high-to-low transition) is received.
SERIAL I/O (SIO) PORT Stop Start D0 D1 D2 D3 D4 D5 D6 D7 D8 Stop 8 Bits of Data Programmable 9th Bit 11-bit Frame A0111-01 Figure 7-5. Serial Port Frames in Mode 2 and 3 7.3.2.3 Mode 3 Mode 3 is the asynchronous, ninth-bit mode. The data frame for this mode is identical to that of mode 2. Mode 3 differs from mode 2 during transmissions in that parity can be enabled, in which case the ninth bit becomes the parity bit.
8XC196MC, MD, MH USER’S MANUAL 7.4 PROGRAMMING THE SERIAL PORT To use the SIO port, you must configure the port pins to serve as special-function signals and set up the SIO channels. 7.4.1 Configuring the Serial Port Pins Before you can use the serial port, you must configure the associated port pins to serve as specialfunction signals. Table 7-1 on page 7-2 lists the pins associated with the serial port.
SERIAL I/O (SIO) PORT Address: Reset State: SPx_CON (Continued) x = 0–1 (8XC196MH) 1F83H, 1F8BH 00H The serial port control (SPx_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. 7 M2 8XC196MH Bit Number 3 0 DIR PAR Bit Mnemonic REN TB8 REN PEN M1 M0 Function Receive Enable Setting this bit enables receptions. When this bit is set, a falling edge on the RXDx pin starts a reception in mode 1, 2, or 3.
8XC196MC, MD, MH USER’S MANUAL 7.4.3 Programming the Baud Rate and Clock Source The SPx_BAUD register (Figure 7-7) selects the clock input for the baud-rate generator and defines the baud rate for all serial I/O modes. (For mode 4 with SCLKx# configured for input, the baud-rate generator is not used.) This register acts as a control register during write operations and as a down-counter monitor during read operations.
SERIAL I/O (SIO) PORT Address: Reset State: SPx_BAUD (Continued) x = 0–1 (8XC196MH) 1F84H, 1F8CH 0000H The serial port baud rate x (SP x_BAUD) register selects the serial port x baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate. The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum BAUD_VALUE is 0000H when using XTAL1 and 0001H when using BCLKx.
8XC196MC, MD, MH USER’S MANUAL CAUTION For mode 0 receptions, the BAUD_VALUE must be 0002H or greater. Otherwise, the resulting data in the receive shift register will be incorrect. The reason for this restriction is that the receive shift register is clocked from an internal signal rather than the signal on TXDx.
SERIAL I/O (SIO) PORT 7.4.5 Determining Serial Port Status You can read the SPx_STATUS register (Figure 7-8) to determine the status of the serial port. Reading SPx_STATUS clears all bits except TXE. For this reason, we recommend that you copy the contents of the SPx_STATUS register into a shadow register and then execute bit-test instructions such as JBC and JBS on the shadow register.
8XC196MC, MD, MH USER’S MANUAL The receiver checks for a valid stop bit. Unless a stop bit is found within the appropriate time, the framing error (FE) bit in the SPx_STATUS register is set. When the stop bit is detected, the data in the receive shift register is loaded into SBUFx_RX and the receive interrupt (RI) flag is set. If this happens before the previous byte in SBUFx_RX is read, the overrun error (OE) bit is set.
8 Frequency Generator
CHAPTER 8 FREQUENCY GENERATOR The 8XC196MD has a peripheral not found on other 8XC196Mx devices — the frequency generator. This peripheral produces a waveform with a fixed duty cycle (50%) and a programmable frequency (ranging from 4 kHz to 1 MHz with a 16-MHz input clock). One application for the frequency generator is to drive an infrared LED to transmit remote control data and control signals. This chapter describes the frequency generator and explains how to configure it.
8XC196MC, MD, MH USER’S MANUAL The frequency register (FREQ_GEN) controls the output frequency. The frequency generator loads the FREQ_GEN value into the counter. The counter counts down until it reaches zero, at which time the value is reloaded from the FREQ_GEN register. Each load toggles the D flip-flop, producing the 50% duty cycle output. The count register (FREQ_CNT) reflects the current value of the down-counter.
FREQUENCY GENERATOR 8.2 PROGRAMMING THE FREQUENCY GENERATOR This section explains how to configure the frequency generator and determine its status. 8.2.1 Configuring the Output The frequency generator’s output is multiplexed with P7.7, so you must configure it as a specialfunction output signal. To do so, follow this sequence: 1. Clear bit 7 of P7_DIR. 2. Set bit 7 of P7_MODE. 3. Clear bit 7 of P7_REG. Refer to Chapter 6, “I/O Ports,” for additional information about configuring port pins. 8.2.
8XC196MC, MD, MH USER’S MANUAL 8.2.3 Determining the Current Value of the Down-counter You can read the FREQ_CNT register (Figure 8-3) to determine the current value of the downcounter. Address: Reset State: FREQ_CNT (8XC196MD) 1FBAH 00H Read the frequency generator count (FREQ_CNT) register to determine the current value of the down-counter. 7 0 8XC196MD Count Bit Number Function 7:0 Count This register contains the current down-counter value. Figure 8-3.
FREQUENCY GENERATOR VCC 8XC196 Device Filter and Detector Output Signal P7.7 A2704-02 Figure 8-4. Infrared Remote Control Application Block Diagram 40 kHz Zero = 2 ms One = 4 ms A2703-01 Figure 8-5. Data Encoding Example This program example was designed to run on an 8XC196MD demo board. It uses an EPA timer (timer 1) and compare channel (COMP3) to provide the timebase for the ones and zeros. $debug $nolist $include (c:\ecm\196mc\mc.
8XC196MC, MD, MH USER’S MANUAL ; followed by a short (1 ms) pause, thus generating a MFM waveform. ; ; This program is assembled to run on the MD demo board. ; ;************************************** ; CONSTANT AND VARIABLE DECLARATIONS ;************************************** ; Program equates ; This section defines the constants used by this program. ; They can be changed at assembly time as required.
FREQUENCY GENERATOR ; temp: temp1: temp2: buf_start: buf_cnt: bit_cnt: flag: dsw dsw dsw dsw dsb dsb dsb 1 1 1 1 1 1 1 ;bit ;bit ;bit ;bit ;bit 0 1 5 6 7 = = = = = zero being sent one being sent get next bit get next byte buffer send in progress ; xmit_buf: dsb buf_size ;block of data to send shift_reg: dsb 1 ; ;***************************** ; MAIN PROGRAM ;***************************** ; Define the program location and set up the interrupts and stack.
8XC196MC, MD, MH USER’S MANUAL stb ei temp,freq_gen[0] ;into freq gen ;enable interrupts ; ; ;***************************************** ; Now send buffer out as serial data bytes ;***************************************** ; This section issues a 1 millisecond pulse on P2.0 ; for use with an oscilloscope monitor. ;***************************************** ; ld wsr,#7EH ld temp,#0400 andb p2_reg_w,#11111110b ;strobe p2.
FREQUENCY GENERATOR dec_buf_cnt: ; get_bit: ; send_zero: cmpb jne ljmp decb buf_cnt,#0 dec_buf_cnt all_done buf_cnt andb flag,#11011111b shlb shift_reg,#1 jc send_one ;see if last byte has been sent ;no! ;yes! ;decrement byte count ;clear get bit flag ;shift MSB into carry flag ;send a one ;else send zero orb ldb ldb add ldb orb ldb sjmp flag,#00000001b ;set zero's flag wsr,#7BH ;set up EPA comp3_con_w,#01000000b comp3_time_w,timer1_w,#zero_time wsr,#7EH p7_mode_w,#10000000b ;start FREQOUT wsr,zero_
9 Waveform Generator
CHAPTER 9 WAVEFORM GENERATOR A waveform generator simplifies the task of generating synchronized, pulse-width modulated (PWM) outputs. This waveform generator is optimized for motion control applications such as driving 3-phase AC induction motors, 3-phase DC brushless motors, or 4-phase stepping motors. The waveform generator can produce three independent pairs of complementary PWM outputs that share a common carrier period, dead time, and operating mode.
8XC196MC, MD, MH USER’S MANUAL Timebase Generator 16 WG_RELOAD Buffer 16 WG_RELOAD Update WG_RELOAD 16 WG_COUNTER = 1 WG Interrupt WG_COUNTER = WG_RELOAD Reload Comparator WG_COUNTER 16 To Other Phase Driver Channels Phase Driver One of Three Channels Dead-time & Output Circuitry Phase Comparator P6.0 / WG1# P6.
WAVEFORM GENERATOR 9.2 WAVEFORM GENERATOR SIGNALS AND REGISTERS Table 9-1 describes the waveform generator’s signals, and Table 9-2 briefly describes the control and status registers. Table 9-1. Waveform Generator Signals Port Pin Waveform Generator Signal Type O Description P6.0 WG1# Waveform generator phase 1 negative output. P6.1 WG1 O Waveform generator phase 1 positive output. P6.2 WG2# O Waveform generator phase 2 negative output. P6.
8XC196MC, MD, MH USER’S MANUAL Table 9-2. Waveform Generator Control and Status Registers (Continued) Mnemonic WG_CONTROL Address 1FCCH Description Waveform Generator Control The control register determines the waveform generator’s operating mode, starts and stops the counter, specifies the dead time for all phases, and indicates the current count direction. WG_COUNTER 1FCAH Waveform Generator Count Value The read-only counter register reflects the current counter value.
WAVEFORM GENERATOR 9.3.2 Phase Driver Channels The phase driver channels determine the duty cycle of the outputs. You specify the duty cycle by writing a value to each phase’s compare register (WG_COMPx). In all operating modes, the outputs are initially asserted, and they remain asserted until the counter value (WG_COUNTER) matches the phase’s compare register (WG_COMPx) value. At this point, the outputs are deasserted and remain deasserted until another event occurs.
8XC196MC, MD, MH USER’S MANUAL The protection circuitry (Figure 9-3) monitors the EXTINT pin. When it detects a valid event on the input, it simultaneously disables the outputs and generates an EXTINT interrupt request. Software can also disable the outputs by clearing the enable outputs (EO) bit in the protection (WG_PROTECT) register. For the 8XC196MC and 8XC196MD, disabled outputs go to their inactive states based on the programmed polarity.
WAVEFORM GENERATOR The WG_RELOAD register is updated when the counter value reaches the reload value. The WG_COUNTER register is loaded with the updated WG_RELOAD value, so a new reload value takes effect for the next cycle. In mode 3 (and mode 4 for the 8XC196MH), the WG_RELOAD register can be updated when an EPA event occurs. This requires you to enable an EPA channel’s peripheral function. (See Chapter 11, “Event Processor Array (EPA)” for details.
8XC196MC, MD, MH USER’S MANUAL Table 9-3. Operation in Center-aligned and Edge-aligned Modes Step Center-aligned Modes Edge-aligned Modes 1 Load WG_COUNTER with WG_RELOAD. Leave outputs deasserted. Load WG_COUNTER with 0001H. Leave outputs deasserted. 2 When counter is enabled, begin counting down. When counter is enabled, begin counting up. Assert outputs when up count begins. When WG_COUNTER reaches 1, wait 1 state, then begin counting up. Assert outputs when up count begins.
WAVEFORM GENERATOR 9.3.5.1 Center-aligned Modes In the center-aligned modes, the counter counts down from the WG_RELOAD value to 1, then counts back up from 1 to WG_RELOAD. When you write to the WG_RELOAD register, WG_COUNTER is loaded with the reload value. When you set the enable bit in the control register, the counter begins counting down and continues counting until it reaches 1, waits one state time, and starts counting up until it reaches WG_RELOAD.
8XC196MC, MD, MH USER’S MANUAL WG_COMPx WG_COUNTER 1 WG_COUNTER =WG_COMPx WG Interrupt P6.0 / WG1# Note: Carrier period and duty cycle both change since WG_COMPx is not changed. P6.1 / WG1 Mode 0, OP0 = OP1 = 1, PH1.0 = PH1.1 = PH1.2 = 1 = Additional interrupt in mode 1 only. A2641-01 Figure 9-5. Center-aligned Modes — Output Operation 9.3.5.2 Edge-Aligned Modes In the edge-aligned modes, the counter begins at 1 and counts up to the WG_RELOAD value.
WAVEFORM GENERATOR WG_RELOAD Value Counter Enabled WG_COUNTER Value 1 EPA Event (Mode 3 Only) WG_RELOAD Updated 0 Carrier Period Reset Write to WG_RELOAD A2639-01 Figure 9-6. Edge-aligned Modes — Counter Operation EPA Event WG_COMPx WG_COUNTER 1 WG_COUNTER =WG_COMP Carrier Period WG Interrupt P6.0 / WG1# Note: Carrier period and duty cycle both change since WG_COMPx is not changed. P6.1 / WG1 Mode 3, OP0 = OP1 = 1, PH1.0 = PH1.1 = PH1.2 = 1 A2653-01 Figure 9-7.
8XC196MC, MD, MH USER’S MANUAL 9.4 PROGRAMMING THE WAVEFORM GENERATOR This section explains how to configure the waveform generator and determine its status. 9.4.1 Configuring the Outputs The waveform generator’s outputs are multiplexed with general-purpose output port 6, so you must configure them as special-function signals to use them as waveform-generator outputs.
WAVEFORM GENERATOR Address: Reset State: WG_OUTPUT (Waveform Generator) 1FC0H 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT. 15 8 OP1 OP0 SYNC PE7 PE6 PH3.2 PH2.2 PH1.2 7 0 P7 Bit Number 15 P6 PH3.1 PH3.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: WG_OUTPUT (Waveform Generator) (Continued) 1FC0H 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT. 15 8 OP1 OP0 SYNC PE7 PE6 PH3.2 PH2.2 PH1.
WAVEFORM GENERATOR 9.4.2 Controlling the Protection Circuitry and EXTINT Interrupt Generation The protection register (Figure 9-9) controls the protection circuitry and EXTINT interrupt requests. Address: Reset State (MC, MD) Reset State (MH): WG_PROTECT 1FCEH F0H E0H The waveform protection (WG_PROTECT) register enables and disables the outputs and the protection circuitry.
8XC196MC, MD, MH USER’S MANUAL 9.4.3 Specifying the Carrier Period and Duty Cycle The reload register (WG_RELOAD) and the phase compare registers (WG_COMPx) control the carrier period and duty cycle. Write a value to the reload register (Figure 9-10) to establish the carrier period. Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted.
WAVEFORM GENERATOR Address: Reset State: WG_COMP x x = 1–3 1FC2H,1FC4H,1FC6H 0000H The phase compare (WG_COMPx) register controls the duty cycle of each phase. Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted. Changing the WG_RELOAD value changes both the carrier period and the duty cycle because the outputs remain asserted for a constant length of time, while the counter takes longer to cycle.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State (MC, MD): Reset State (MH): WG_CONTROL 1FCCH 00C0H 8000H The waveform generator control (WG_CONTROL) register controls the operating mode, dead time, and count direction, and enables and disables the counter. 15 8 — M2 M1 M0 CS EC DT9 DT8 7 0 DT7 Bit Number DT6 DT5 DT4 DT3 Bit Mnemonic 15 — 14:12 M2:0 DT2 DT1 DT0 Function Reserved; for compatibility with future devices, write zero to this bit.
WAVEFORM GENERATOR 9.5 DETERMINING THE WAVEFORM GENERATOR’S STATUS Read WG_CONTROL (Figure 9-12 on page 9-18) to determine the current dead-time value, counter status, count direction, and operating mode. Read WG_COUNTER (Figure 9-13) to determine the current counter value. Address: Reset State (MC, MD): Reset State (MH): WG_COUNTER 1FCAH XXXXH 0000H You can read the waveform generator counter (WG_COUNTER) register to determine the current counter value.
8XC196MC, MD, MH USER’S MANUAL To enable the interrupts, set the corresponding mask bits in the mask register (see Table 9-2 on page 9-3) and execute the EI instruction to enable interrupt servicing. You can read the interrupt pending register to determine whether there are any pending interrupts. Refer to Chapter 5, “Standard and PTS Interrupts” for details. 9.7 DESIGN CONSIDERATIONS This section describes design and programming considerations for using the waveform generator. 9.7.
WAVEFORM GENERATOR 9.7.2 EXTINT Interrupts and Protection Circuitry The protection register contains two bits, disable protection (DP) and enable output (EO), that together enable and disable the waveform generator’s outputs. The EXTINT event generates a single short pulse that clears the EO bit, so if software sets the EO bit immediately following an EXTINT event, the outputs will be disabled only for the time between the EXTINT event and the CPU write.
8XC196MC, MD, MH USER’S MANUAL ph3: dsw 1 ;P6.
WAVEFORM GENERATOR ;load WFG registers ; call wgout ;initialize WG_OUTPUT register call loadregs ;initialize reload & compare regs call protect ;initialize protection call wgcon ;initialize WG_CONTROL ; ;enable interrupts & loop here ; ei sjmp $ ; ;**************************************** ; form WG_OUTPUT value from variable data ;**************************************** ; wgout: ld temp,op1 ;get op1 and temp,#0001h ;mask shl temp,#15 ;move bit to correct location ld and shl or temp1,op0 temp1,#0001h temp
8XC196MC, MD, MH USER’S MANUAL or temp1,temp ;combine ld and shl or temp,p6 temp,#0001h temp,#6 temp1,temp ;get p6 bit ;mask ;move to correct location ;combine ld and shl or temp,ph3 temp,#0003h temp,#4h temp1,temp ;get ph3 bits again ;mask for ph3.0 & 1 ;move ;combine1 ld and shl or temp,ph2 temp,#0003h temp,#2h temp1,temp ;get ph2 bits again ;mask for ph2.0 & 1 ;move ;combine ld and or temp,ph1 temp,#0003h temp1,temp ;get ph1 bits again ;mask for ph3.
WAVEFORM GENERATOR and shl temp,#0001h temp,#3 ;mask ;shift to correct location ld and shl or temp1,it temp1,#0001h temp1,#2 temp,temp1 ;interrupt type bit ;mask ;shift to correct location ;combine into temp ld and shl or temp1,dp temp1,#0001h temp1,#1 temp,temp1 ;disable protection bit ;mask ;shift to correct location ;combine into temp ld and or temp1,eo temp1,#0001h temp,temp1 ;enable output bit ;mask ;combine into temp stb ret temp,WG_PROTECT[0];store byte into WG_PROTECT ; ;*************
10 Pulse-width Modulator
CHAPTER 10 PULSE-WIDTH MODULATOR The pulse-width modulator (PWM) module has two output pins, each of which can output a PWM signal with a fixed, programmable frequency and a variable duty cycle. These outputs can be used to drive motors that require an unfiltered PWM waveform for optimal efficiency, or they can be filtered to produce a smooth analog signal.
8XC196MC, MD, MH USER’S MANUAL 8 Load Buffer PWMx_CONTROL 8 Bufferx 8 = Comparatorx RS Flip-flopx 8 Port 6 Control R Q Internal Clock Signal PWM_COUNT S Count = 00H WG_OUT PWMx Output Down Counter P6.x/PWMx 8 8 PWM_PERIOD Load Shared Circuitry A2761-02 Figure 10-1. PWM Block Diagram 10.2 PWM SIGNALS AND REGISTERS Table 10-1 describes the PWM’s signals and Table 10-2 briefly describes the control and status registers. Table 10-1.
PULSE-WIDTH MODULATOR Table 10-2. PWM Control and Status Registers Mnemonic Address PWM0_CONTROL PWM1_CONTROL 1FB0H 1FB2H PWM_PERIOD 1FB4H Description PWM Duty Cycle This register controls the PWM duty cycle. A zero loaded into this register will cause the PWM to output a low continuously (0% duty cycle). An FFH in this register will cause the PWM to have its maximum duty cycle (99.6% duty cycle). PWM Period This register holds a programmed value that determines the output period of the PWM outputs.
8XC196MC, MD, MH USER’S MANUAL The counter counts down to 00H, at which time the PWM output is driven high, the counter value is reloaded from the PWM_PERIOD register, and the contents of the control registers are loaded into the buffers. The PWM output remains high until the counter value matches the value in the buffer, at which time the output is pulled low. You can read the count register (PWM_COUNT) to see the current value of the counter. When the counter resets again (i.e.
PULSE-WIDTH MODULATOR where: PWM_PERIOD = 8-bit value to load into the PWM_PERIOD register FXTAL1 = input frequency on XTAL1 pin, in MHz TPWM = output period on the PWM output pins, in µs FPWM = output frequency on the PWM output pins, in MHz Table 10-3. PWM Output Frequencies (FPWM) XTAL1 Frequency (FXTAL 1) PWM_PERIOD 8 MHz 10 MHz 16 MHz 00H 15.6 kHz 19.5 kHz 31.2 kHz 0FH 976.6 Hz 1220.7 Hz 1953.1 Hz 1FH 488.3 Hz 610.3 Hz 976.6 Hz 2FH 325.5 Hz 406.9 Hz 651.0 Hz 3FH 244.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: PWM_PERIOD 1FB4H 00H The PWM period (PWM_PERIOD) register controls the period of the PWM outputs. It contains a value that determines the number of state counts necessary for incrementing the PWM counter. The value of PWM_PERIOD is loaded into the PWM period count register whenever the count equals zero. 7 0 PWM Period Bit Number 7:0 Function PWM Period This register controls the period of the PWM outputs.
PULSE-WIDTH MODULATOR Address: PWMx_CONTROL x = 0–1 Reset State: Table 10-2 on page 10-3 00H The PWM control (PWMx_CONTROL) register determines the duty cycle of the PWM x channel. A zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in this register causes the PWM to have its maximum duty cycle (99.6% duty cycle). 7 0 PWM Duty Cycle Bit Number 7:0 Function PWM Duty Cycle This register controls the PWM duty cycle.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: PWM_COUNT (read only) 1FB6H 00H The PWM count (PWM_COUNT) register provides the current value of the decremented period counter. 7 0 PWM Count Value Bit Number 7:0 Function PWM Count Value This register contains the current value of the decremented period counter. Figure 10-5. PWM Count (PWM_COUNT) Register 10.5.
PULSE-WIDTH MODULATOR Address: Reset State: WG_OUTPUT (Waveform Generator) 1FC0H 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT. 15 8 OP1 OP0 SYNC PE7 PE6 PH3.2 PH2.2 PH1.2 7 0 P7 Bit Number P6 PH3.1 PH3.
8XC196MC, MD, MH USER’S MANUAL 10.5.4 Generating Analog Outputs PWM modules can generate a rectangular pulse train that varies in duty cycle and period. Filtering this output will create a smooth analog signal. To make a signal swing over the desired analog range, first buffer the signal and then filter it with either a simple RC network or an active filter. Figure 10-7 is a block diagram of the type of circuit needed to create the smooth analog signal.
11 Event Processor Array (EPA)
CHAPTER 11 EVENT PROCESSOR ARRAY (EPA) Control applications often require high-speed event control. For example, the controller may need to periodically generate pulse-width modulated outputs or an interrupt. In another application, the controller may monitor an input signal to determine the status of an external device. The event processor array (EPA) was designed to reduce the CPU overhead associated with these types of event control.
8XC196MC, MD, MH USER’S MANUAL Timer-counter Unit TIMER1 TIMER2 EPA0 Capture/Compare Channel 0 EPAx Capture/Compare Channel x EPA0 Interrupt .. . EPAx Interrupt Compare-only Channel 0 COMP0 Interrupt Compare-only Channel y COMPy Interrupt COMP0 .. . COMPy Notes: For the 8XC196MC, x & y = 3. For the 8XC196MD, x & y = 5. For the 8XC196MH, x = 1 & y = 3. A2846-01 Figure 11-1. EPA Block Diagram 11.
EVENT PROCESSOR ARRAY (EPA) Table 11-2. EPA and Timer/Counter Signals (Continued) Port Pin 8XC196MC 8XC196MD 8XC196MH P2.4 P2.5 P2.6 P2.7 — — P2.4 P2.5 P2.6 P2.7 P7.2 P7.3 P2.4 P2.5 P2.6 P2.3 — — EPA Signals COMP0 COMP1 COMP2 COMP3 COMP4 COMP5 EPA Signal Type Description O Output of the compare-only channels. Table 11-3.
8XC196MC, MD, MH USER’S MANUAL Table 11-3. EPA Control and Status Registers (Continued) Address Mnemonic INT_PEND Description MC MD 0009H 0009H MH 0009H Interrupt Pending Any set bit in this 8-bit register indicates a pending interrupt request. INT_PEND1 0012H 0012H 0012H Interrupt Pending 1 Any set bit in this 8-bit register indicates a pending interrupt request.
EVENT PROCESSOR ARRAY (EPA) Table 11-3. EPA Control and Status Registers (Continued) Address Mnemonic PI_MASK Description MC MD MH 1FBCH 1FBCH 1FBCH Peripheral Interrupt Mask The bits in this register enable and disable (mask) the timer 1 and 2 overflow/underflow interrupt requests, the waveform generator interrupt request (MC, MD), the EPA compare-only channel 5 interrupt request ( MD), and the serial port error interrupts (MH).
8XC196MC, MD, MH USER’S MANUAL T2CONTROL.2:0 3 Timer 2 FXTAL1/4 Prescaler Module Clock Overflow/ Underflow Timer 1 Overflow/Underflow TIMER2 T2CONTROL.6 Direction OVRTM Interrupt T1CONTROL.2:0 3 Timer 1 FXTAL1/4 Prescaler Module T1CLK Clock Overflow/ Underflow Quadrature Count TIMER1 T1DIR T1RELOAD Direction T1CONTROL.6 Quadrature Direction A3131-01 Figure 11-2.
EVENT PROCESSOR ARRAY (EPA) where: prescaler_divisor is the clock prescaler divisor from the TxCONTROL registers (see “Timer 1 Control (T1CONTROL) Register” on page 11-16 and “Timer 2 Control (T2CONTROL) Register” on page 11-17). FXTAL1 is the input frequency on XTAL1. 11.3.1 Cascade Mode (Timer 2 Only) Timer 2 can be used in cascade mode. In this mode, the timer 1 overflow output is used as the timer 2 clock input.
8XC196MC, MD, MH USER’S MANUAL Increment MCS® 96 Microcontroller Decrement PH2 X PH1 Y T1CLK Optical Reader T1DIR D Q D Q D Q X_internal D Q D Q D Q Y_internal A1550-01 Figure 11-3. Quadrature Mode Interface Table 11-4.
EVENT PROCESSOR ARRAY (EPA) CLKOUT† PH2 T1CLK T1DIR COUNT x x+1 x +2 x +3 x +4 x +5 x +6 x +5 x +4 x +3 x +2 x +1 † CLKOUT is available on the 8XC196MC and 8XC196MD only. A1549-01 Figure 11-4. Quadrature Mode Timing and Count 11.4 EPA CHANNEL FUNCTIONAL OVERVIEW The EPA has both programmable capture/compare and compare-only channels. Each capture/compare channel can perform the following tasks.
8XC196MC, MD, MH USER’S MANUAL Each EPA channel has a control register, EPAx_CON (capture/compare channels) or COMPx_CON (compare-only channels); an event-time register, EPAx_TIME (capture/compare channels) or COMPx_TIME (compare-only channels); and a timer input (Figure 11-5). The control register selects the timer, the mode, and either the event to be captured or the event that is to occur. The event-time register holds the captured timer value in capture mode and the event time in compare mode.
EVENT PROCESSOR ARRAY (EPA) TIMERx Event Occurs at EPA Pin Capture Buffer EPA Interrupt Pending Bit Set EPAx_TIME Read-out Time Value A2458-02 Figure 11-6. EPA Simplified Input-capture Structure If a third event occurs before the CPU reads the event-time register, the overwrite bit (EPAx_CON.0) determines how the EPA will handle the event. If the bit is clear, the EPA ignores the third event. If the bit is set, the third event time overwrites the second event time in the capture buffer.
8XC196MC, MD, MH USER’S MANUAL Table 11-5. Action Taken When a Valid Edge Occurs Overwrite Bit (EPAx_CON.0) Status of Capture Buffer & EPAx_TIME 0 empty Edge is captured and event time is loaded into the capture buffer and EPAx_TIME register. 0 full New data is ignored — no capture, EPA interrupt, or transfer occurs. 1 empty Edge is captured and event time is loaded into the capture buffer and EPAx_TIME register.
EVENT PROCESSOR ARRAY (EPA) 11.4.1.2 Preventing EPA Overruns Any one of the following methods can be used to prevent or recover from an EPA overrun situation. • Clear EPAx_CON.0 When the overwrite bit (EPAx_CON.0) is zero, the EPA does not consider the captured edge until the EPAx_TIME register is read and the data in the capture buffer is transferred to EPAx_TIME. This prevents overruns by ignoring new input capture events when both the capture buffer and EPAx_TIME contain valid capture times.
8XC196MC, MD, MH USER’S MANUAL The maximum output frequency depends upon the total interrupt latency and the interrupt-service execution times used by your system. As additional EPA channels and the other functions of the microcontroller are used, the maximum PWM frequency decreases because the total interrupt latency and interrupt-service execution time increases.
EVENT PROCESSOR ARRAY (EPA) With this method, the resolution of the EPA (selected by the TxCONTROL registers; see Figure 11-8 on page 11-16 and Figure 11-9 on page 11-17) determines the maximum PWM output frequency. (Resolution is the minimum time required between consecutive captures or compares.) When the input frequency on XTAL1 is 16 MHz, a 250 ns resolution results in a maximum PWM of 4 MHz. 11.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: T1CONTROL 1F78H 00H The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
EVENT PROCESSOR ARRAY (EPA) Address: Reset State: T2CONTROL 1F7CH 00H The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
8XC196MC, MD, MH USER’S MANUAL 11.5.3 Programming the Capture/Compare Channels The EPAx_CON register controls the function of its assigned capture/compare channel. The registers are identical with the exception of bit 2. For EPA channels 0, 2, and 4, setting this bit enables an EPA event to cause a waveform generator reload. For EPA channels 1, 3, and 5, setting this bit enables an EPA event to cause an A/D conversion.
EVENT PROCESSOR ARRAY (EPA) Address: Reset State: EPAx_CON x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) See Table 11-3 on page 11-3 00H The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT ON/RT TB CE M1 M0 RE AD ROT ON/RT 7 x = 1, 3, 5 Bit Number 7 0 Bit Mnemonic TB Function Time Base Select Specifies the reference timer.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: EPAx_CON (Continued) x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) See Table 11-3 on page 11-3 00H The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT ON/RT TB CE M1 M0 RE AD ROT ON/RT 7 x = 1, 3, 5 Bit Number 3 0 Bit Mnemonic RE Function Re-enable Re-enable applies to the compare mode only.
EVENT PROCESSOR ARRAY (EPA) Address: Reset State: EPAx_CON (Continued) x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) See Table 11-3 on page 11-3 00H The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT ON/RT TB CE M1 M0 RE AD ROT ON/RT 7 x = 1, 3, 5 Bit Number 1 0 Bit Mnemonic ROT Function Reset Opposite Timer Controls different functions for capture and compare modes.
8XC196MC, MD, MH USER’S MANUAL 11.5.4 Programming the Compare-only Channels To program a compare event, you must first write to the COMPx_CON register (Figure 11-11) to configure the compare-only channel and then load the event time into COMPx_TIME. COMPx_CON has the same bits and settings as EPAx_CON. COMPx_TIME is functionally identical to EPAx_TIME.
EVENT PROCESSOR ARRAY (EPA) COMPx_CON (Continued) x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD) Address: Reset State: See Table 11-3 on page 11-3 00H The EPA compare control (COMPx_CON) registers determine the function of the EPA compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT RT TB CE M1 M0 RE AD ROT RT 7 x = 1, 3, 5 2 WGR AD 0 A/D Conversion, Waveform Generator Reload The function of this bit depends on the EPA channel.
8XC196MC, MD, MH USER’S MANUAL 11.7 DETERMINING EVENT STATUS In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event (even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx_TIME register.
12 Analog-to-digital Converter
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CHAPTER 12 ANALOG-TO-DIGITAL (A/D) CONVERTER The analog-to-digital (A/D) converter can convert an analog input voltage to a digital value and set the A/D interrupt pending bit when it stores the result. It can also monitor a pin and set the A/D interrupt pending bit when the input voltage crosses over or under a programmed threshold voltage. This chapter describes the A/D converter and explains how to program it. 12.
8XC196MC, MD, MH USER’S MANUAL 12.2 A/D CONVERTER SIGNALS AND REGISTERS Table 12-1 lists the A/D signals and Table 12-2 describes the control and status registers. Although the analog inputs are multiplexed with I/O port pins, no configuration is necessary. Table 12-1. A/D Converter Pins Port Pin A/D Signal A/D Signal Type Description P1.4:0 P1.5:0 ACH12:8 (MC) ACH13:8 (MD) I Analog inputs. See the “Voltage on Analog Input Pin” specification in the datasheet. P0.
ANALOG-TO-DIGITAL (A/D) CONVERTER Table 12-2. A/D Control and Status Registers (Continued) Mnemonic P0_PIN P1_PIN (MC,MD) Address Description 1FA8H (MC, MD) 1FDAH (MH) Port 0 Pin State 1FA9H (MC, MD) Port 1 Pin State Read P0_PIN to determine the current values of the port 0 pins. Reading the port induces noise into the A/D converter, decreasing the accuracy of any conversion in progress. We strongly recommend that you not read the port while an A/D conversion is in progress.
8XC196MC, MD, MH USER’S MANUAL Once the A/D converter receives the command to start a conversion, a delay time elapses before sampling begins. (EPA-initiated conversions begin after the capture/compare event. Immediate conversions, those initiated directly by a write to AD_COMMAND, begin within three state times after the instruction is completed.) During this sample delay, the hardware clears the successive approximation register and selects the designated multiplexer channel.
ANALOG-TO-DIGITAL (A/D) CONVERTER 12.4.1 Programming the A/D Test Register The AD_TEST register (Figure 12-2) analog specifies an offset voltage to be applied to the resistor ladder. To use the zero-offset adjustment, first perform two conversions, one on ANGND and one on VREF. With the results of these conversions, use a software routine to calculate the zerooffset error. Specify the zero-offset adjustment by writing the appropriate value to AD_TEST.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State (MC, MD): Reset State (MH): AD_RESULT (Write) 1FAAH FFC0H 7FC0H The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes. 15 8 REFV7 REFV6 REFV5 REFV4 REFV3 REFV2 REFV1 REFV0 — — — — — — — — 7 0 Bit Number 15:8 Bit Mnemonic REFV7:0 Function Reference Voltage These bits specify the threshold value.
ANALOG-TO-DIGITAL (A/D) CONVERTER Address: Reset State: AD_TIME 1FAFH FFH The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit. This register programs the speed at which the A/D can run — not the speed at which it can convert correctly. Consult the data sheet for recommended values. Initialize the AD_TIME register before initializing the AD_COMMAND register. Do not write to this register while a conversion is in progress; the results are unpredictable.
8XC196MC, MD, MH USER’S MANUAL Address: Reset State: AD_COMMAND 1FACH 80H The A/D command (AD_COMMAND) register selects the A/D channel number to be converted, controls whether the A/D converter starts immediately or with an EPA command, and selects the conversion mode. 7 0 — Bit Number M1 M0 GO ACH3 Bit Mnemonic 7 — 6:5 M1:0 ACH2 ACH1 ACH0 Function Reserved; for compatibility with future devices, write zeros to these bits. A/D Mode† These bits determine the A/D mode.
ANALOG-TO-DIGITAL (A/D) CONVERTER 12.5 DETERMINING A/D STATUS AND CONVERSION RESULTS You can read the AD_RESULT register (Figure 12-6) to determine the status of the A/D converter. The AD_RESULT register is cleared when a new conversion is started; therefore, to prevent losing data, you must read both bytes before a new conversion starts. If you read AD_RESULT before the conversion is complete, the result is not guaranteed to be accurate.
8XC196MC, MD, MH USER’S MANUAL 12.6 DESIGN CONSIDERATIONS This section describes considerations for the external interface circuitry and describes the errors that can occur in any A/D converter. The datasheet lists the absolute error specification, which includes all deviations between the actual conversion process and an ideal converter. However, because the various components of error are important in many applications, the datasheet also lists the specific error components.
ANALOG-TO-DIGITAL (A/D) CONVERTER Typically, the (RF / AV + 1) term is the major contributor to the total resistance and the factor that determines the minimum sample time specified in the datasheet. 12.6.1.1 Minimizing the Effect of High Input Source Resistance Under some conditions, the input source resistance (RSOURCE) can be great enough to affect the measurement. You can minimize this effect by increasing the sample time or by connecting an external capacitor (CEXT) from the input pin to ANGND.
8XC196MC, MD, MH USER’S MANUAL 12.6.1.2 Suggested A/D Input Circuit The suggested A/D input circuit shown in Figure 12-8 provides limited protection against overvoltage conditions on the analog input. Should the input voltage be driven significantly below ANGND or above VREF, diode D2 or D1 will forward bias at about 0.8 volts. The device’s input protection begins to turn on at approximately 0.5 volts beyond ANGND or VREF.
ANALOG-TO-DIGITAL (A/D) CONVERTER ANGND should be within about ± 50 mV of VSS. VREF should be well regulated and used only for the A/D converter. The VREF supply can be between 4.5 and 5.5 volts and must be able to source approximately 5 mA (see the datasheet for actual specifications). VREF should be approximately the same voltage as VCC. VREF and VCC should power up at the same time, to avoid potential latch-up conditions on VREF.
8XC196MC, MD, MH USER’S MANUAL In many applications, it is less critical to record the absolute accuracy of an input than it is to detect that a change has occurred. This approach is acceptable as long as the converter is monotonic and has no missing codes. That is, increasing input voltages produce adjacent, unique output codes that are also increasing. Decreasing input voltages produce adjacent, unique output codes that are also decreasing.
ANALOG-TO-DIGITAL (A/D) CONVERTER 7 FINAL CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO (Vref – 1.5 (LSB)). 6 5 ACTUAL CHARACTERISTIC OF AN IDEAL A/D CONVERTER Ø OUTPUT CODE, Q 4 THE VOLTAGE CHANGE BETWEEN THE ADJACENT CODE TRANSITIONS (THE “CODE WIDTH”) IS = 1 LSB. 3 2 1 FIRST CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO 1/2 LSB. 0 1/2 1 2 3 4 5 6 6 1/2 7 8 INPUT VOLTAGE (LSBs) A0083-01 Figure 12-9.
8XC196MC, MD, MH USER’S MANUAL 7 FULL SCALE ERROR 6 IDEAL CHARACTERISTIC 5 ACTUAL CHARACTERISTIC ABSOLUTE ERROR Ø OUTPUT CODE, Q 4 3 2 1 ZERO OFFSET 0 1/2 1 2 3 4 5 6 6 1/2 7 8 INPUT VOLTAGE (LSBs) A0084-01 Figure 12-10. Actual and Ideal A/D Conversion Characteristics The actual characteristic of a hypothetical 3-bit converter is not perfect.
ANALOG-TO-DIGITAL (A/D) CONVERTER Differential nonlinearity is the degree to which actual code widths differ from the ideal one-LSB width. It provides a measure of how much the input voltage may have changed in order to produce a one-count change in the conversion result. In the 10-bit converter, the code widths are ideally 5 mV (VREF / 1024).
8XC196MC, MD, MH USER’S MANUAL 7 IDEAL FULL-SCALE CODE TRANSITION 6 IDEAL STRAIGHT LINE TRANSFER FUNCTION 5 ACTUAL FULL-SCALE CODE TRANSITION DIFFERENTIAL NON-LINEARITY (POSITIVE) TERMINAL BASED CHARACTERISTIC (corrected for zero-offset and full-scale error) Ø OUTPUT CODE, Q IDEAL CODE WIDTH 4 ACTUAL CHARACTERISTIC 3 NON-LINEARITY 2 DIFFERENTIAL NON-LINEARITY (NEGATIVE) 1 IDEAL CODE WIDTH ACTUAL FIRST TRANSITION IDEAL FIRST TRANSITION 0 1/2 1 2 3 4 5 6 6 1/2 7 8 INPUT VOLTAGE (LSBs)
13 Minimum Hardware Considerations
CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS The 8XC196MC, MD, and MH have several basic requirements for operation within a system. This chapter describes options for providing the basic requirements and discusses other hardware considerations. 13.1 MINIMUM CONNECTIONS Table 13-1 lists the signals that are required for the device to function and Figure 13-1 shows the connections for a minimum configuration. Table 13-1.
8XC196MC, MD, MH USER’S MANUAL Table 13-1. Minimum Required Signals (Continued) Signal Name XTAL1 Type I Description Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal (MC/MD only). When using an external clock or crystal, instead of the on-chip oscillator, connect the clock input to XTAL1.
MINIMUM HARDWARE CONSIDERATIONS (Note 1) 20 pF VCC XTAL2 VCC 20 pF XTAL1 RESET# (Note 2) 0.01 µF VCC VCC + 4.7 µF VSS EA# NMI 1M BUSWIDTH VPP (Note 3) VCC VCC + READY 1 µF VREF + 1 µF ANGND BHE# RD# WR# Input-only Port Pins (Note 5) Port 5 / Bus Control (Note 4) INST ALE 8XC196 Device Notes: 1. See the datasheet for the oscillator frequency range (FXTAL1) and the crystal manufacturer's datasheet for recommended load capacitors. 2.
8XC196MC, MD, MH USER’S MANUAL 13.2 APPLYING AND REMOVING POWER When power is first applied to the device, RESET# must remain continuously low for at least one state time after the power supply is within tolerance and the oscillator/clock has stabilized; otherwise, operation might be unpredictable. Similarly, when powering down a system, RESET# should be brought low before VCC is removed; otherwise, an inadvertent write to an external location might occur.
MINIMUM HARDWARE CONSIDERATIONS If the A/D converter will be used, connect VREF to a separate reference supply to minimize noise during A/D conversions. Even if the A/D converter will not be used, VREF and ANGND must be connected to provide power to port 0. On the 8XC196MC and MD, they also provide power to port 1. Refer to “Analog Ground and Reference Voltages” on page 12-12 for a detailed discussion of A/D power and ground recommendations.
8XC196MC, MD, MH USER’S MANUAL Figure 13-4 shows the connections between the external crystal and the device. When designing an external oscillator circuit, consider the effects of parasitic board capacitance, extended operating temperatures, and crystal specifications. Consult the manufacturer’s datasheet for performance specifications and required capacitor values. With high-quality components, 20 pF load capacitors (CL) are usually adequate for frequencies above 1 MHz.
MINIMUM HARDWARE CONSIDERATIONS 13.5 USING AN EXTERNAL CLOCK SOURCE To use an external clock source, apply a clock signal to XTAL1 and let XTAL2 float (Figure 13-5). To ensure proper operation, the external clock source must meet the minimum high and low times (TXHXX and TXLXX) and the maximum rise and fall transition times (TXLXH and TXHXL) (Figure 13-6).
8XC196MC, MD, MH USER’S MANUAL 13.6 RESETTING THE DEVICE Reset forces the device into a known state. As soon as RESET# is asserted, the I/O pins, the control pins, and the registers are driven to their reset states. (Tables in Appendix B list the reset states of the pins (see Table B-8 on page B-23 for the 8XC196MC and 8XC196MD or Table B-9 on page B-25 for the 8XC196MH). See Table C-2 on page C-2 for the reset values of the SFRs.) The device remains in its reset state until RESET# is deasserted.
MINIMUM HARDWARE CONSIDERATIONS The 8XC196MH provides the option of an internal-only reset or an internal reset that is also reflected externally (by the RESET# pin). The GEN_CON register controls whether an internal reset asserts the external RESET# signal and indicates the source of the most recent reset. Figure 13-8 describes the general configuration register, GEN_CON.
8XC196MC, MD, MH USER’S MANUAL Internal Internal Reset Signal VCC Clock Reset State Machine External RRST† Trigger Count Complete RESET# CLR ~200 Ω Q Q1 GEN_CON.0 SET (MH Only) RST Instruction WDT Overflow IDLPD Invalid Key † See the datasheet for minimum and maximum RRST values. A3086-01 Figure 13-9. Internal Reset Circuitry 13.6.
MINIMUM HARDWARE CONSIDERATIONS RESET# + 4.7 µF MCS® 96 Microcontroller A0276-02 Figure 13-10. Minimum Reset Circuit Other devices in the system may not be reset because the capacitor will keep the voltage above VIL. Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer the system-reset pulse. Figure 13-11 shows an example of a system-reset circuit. In this example, D2 creates a wired-OR gate connection to the reset pin.
8XC196MC, MD, MH USER’S MANUAL 13.6.2 Issuing the Reset (RST) Instruction The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times. It also clears the processor status word (PSW), sets the master program counter (PC) to 2080H, and resets the special function registers (SFRs). See Table C-2 on page C-2 for the reset values of the SFRs. Putting pull-ups on the address/data bus causes unimplemented areas of memory to be read as FFH.
MINIMUM HARDWARE CONSIDERATIONS You must write two consecutive bytes to the watchdog register (location 0AH) to clear it. For the 8XC196MC and MD, the first byte must be 1EH and the second must be E1H. For the 8XC196MH, the first byte must also be 1EH; however, the second byte can be one of four values. The second byte determines the reset interval (Table 13-3).
14 Special Operating Modes
CHAPTER 14 SPECIAL OPERATING MODES The 8XC196MC, MD, and MH provide two power saving modes: idle and powerdown. They also provide an on-circuit emulation (ONCE) mode that electrically isolates the device from the other system components. This chapter describes each mode and explains how to enter and exit each.
8XC196MC, MD, MH USER’S MANUAL Table 14-1. Operating Mode Control Signals (Continued) Signal Name Port Pin P5.4 Type ONCE# I Description On-circuit Emulation Holding ONCE# low during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. This mode puts all pins, except XTAL1 and XTAL2, into a high-impedance state, thereby isolating the device from other components in the system. The value of ONCE# is latched when the RESET# pin goes inactive.
SPECIAL OPERATING MODES Table 14-2. Operating Mode Control and Status Registers (Continued) Mnemonic Address Description P1_DIR (MH) P2_DIR P5_DIR P7_DIR (MD) 1F9BH 1FD2H 1FF3H 1FD3H Port x Direction P1_MODE(MH) P2_MODE P5_MODE P7_MODE(MD) 1F99H 1FD0H 1FF1H 1FD1H Port x Mode P1_REG (MH) P2_REG P5_REG P7_REG (MD) 1F9DH 1FD4H 1FF5H 1FD5H Port x Data Output Each bit of Px_DIR controls the direction of the corresponding pin.
8XC196MC, MD, MH USER’S MANUAL Disable Clock Input (Powerdown) FXTAL1 XTAL1 Divide-by-two Circuit Disable Clocks (Powerdown) XTAL2 Peripheral Clocks (PH1, PH2) Disable Oscillator (Powerdown) Clock Generators CLKOUT CPU Clocks (PH1, PH2) Disable Clocks (Idle, Powerdown) NOTE: The CLKOUT pin is unique to the 8XC196MC and MD. A3115-02 Figure 14-1. Clock Control During Power-saving Modes 14.3 IDLE MODE In idle mode, the device’s power consumption decreases to approximately 40% of normal consumption.
SPECIAL OPERATING MODES The device enters idle mode after executing the IDLPD #1 instruction. Any enabled interrupt source, either internal or external, or a hardware reset can cause the device to exit idle mode. When an interrupt occurs, the CPU clocks restart and the CPU executes the corresponding interrupt service or PTS routine. When the routine is complete, the CPU fetches and then executes the instruction that follows the IDLPD #1 instruction.
8XC196MC, MD, MH USER’S MANUAL 14.4.2 Entering Powerdown Mode Before entering powerdown, complete the following tasks: • Complete all serial port transmissions or receptions. Otherwise, when the device exits powerdown, the serial port activity will continue where it left off and incorrect data may be transmitted or received. • Complete all analog conversions. If powerdown occurs during the conversion, the result will be incorrect.
SPECIAL OPERATING MODES 14.4.3.3 Asserting the External Interrupt Signal The final way to exit powerdown mode is to assert the external interrupt signal (EXTINT) for at least 50 ns. Although EXTINT is normally a sampled input, the powerdown circuitry uses it as a level-sensitive input. The interrupt need not be enabled to bring the device out of powerdown, but the pin must be configured as a special-function input (see “Bidirectional Port Pin Configurations” on page 6-9).
8XC196MC, MD, MH USER’S MANUAL VCC 8XC196 Device R1 1 MΩ Typical VPP C1 1µF Typical A0279-01 Figure 14-3. External RC Circuit During normal operation (before entering powerdown mode), an internal pull-up holds the VPP pin at VCC. When an external interrupt signal is asserted, the internal oscillator circuitry is enabled and turns on a weak internal pull-down. This weak pull-down causes the external capacitor (C1) to begin discharging at a typical rate of 200 µA.
SPECIAL OPERATING MODES 5 4 EXTINT 3 200 µA C1 Discharge VPP, Volts R1 x C1 Recovery Time Constant 2 Pullup On Code Execution Resumes 1 2 4 6 8 10 12 14 Time, ms 16 18 20 22 A0151-01 Figure 14-4. Typical Voltage on the VPP Pin While Exiting Powerdown Select a resistor that will not interfere with the discharge current. In most cases, values between 200 kΩ and 1 MΩ should perform satisfactorily.
8XC196MC, MD, MH USER’S MANUAL When selecting the capacitor, determine the worst-case discharge time needed for the oscillator to stabilize, then use this formula to calculate an appropriate value for C1.
SPECIAL OPERATING MODES Holding the ONCE# signal low during the rising edge of RESET# causes the device to enter ONCE mode. To prevent accidental entry into ONCE mode, we highly recommend configuring this pin as an output. If you choose to configure this pin as an input, always hold it high during reset and ensure that your system meets the VIH specification (see datasheet) to prevent inadvertent entry into ONCE mode.
15 Interfacing with External Memory
CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY The microcontroller can interface with a variety of external memory devices. It supports either a fixed 8-bit data bus width, a fixed 16-bit data bus width, or a dynamic 8-bit/16-bit data bus width; internal control of wait states for slow external memory devices; and several bus-control modes. These features provide a great deal of flexibility when interfacing with external memory systems.
8XC196MC, MD, MH USER’S MANUAL Table 15-1. External Memory Interface Signals (Continued) Signal Name ALE Port Pin P5.0 Type O Description Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. ALE differs from ADV# in that it does not remain active during the entire bus cycle.
INTERFACING WITH EXTERNAL MEMORY Table 15-1. External Memory Interface Signals (Continued) Signal Name EA# Port Pin — Type I Description External Access This input determines whether memory accesses to special-purpose and program memory partitions are directed to internal or external memory. (See Table 4-1 on page 4-2 for address ranges of specialpurpose and program memory partitions.) These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low.
8XC196MC, MD, MH USER’S MANUAL Table 15-1. External Memory Interface Signals (Continued) Signal Name WRH# Port Pin P5.5 Type O Description Write High† During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. † WRL# P5.2 O The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
INTERFACING WITH EXTERNAL MEMORY Table 15-2. External Memory Interface Registers (Continued) Register Mnemonic P5_REG Address 1FF5H Description Port 5 Data Output For an input, regardless of the pin’s configuration, set the corresponding P5_REG bit. For an output, write the data to be driven out by each pin to the corresponding bit of P5_REG. When a pin is configured as standard I/O (P5_MODE.y = 0), the result of a CPU write to P5_REG is immediately visible on the pin.
8XC196MC, MD, MH USER’S MANUAL When the microcontroller returns from reset, the bus controller fetches the CCBs and loads them into the CCRs. From this point, these CCR bit values define the chip configuration until the microcontroller is reset again. The CCR bits are described in Figures 15-1 and 15-2. (Refer to Chapter 16, “Programming the Nonvolatile Memory,” for descriptions of the methods for programming the CCBs.
INTERFACING WITH EXTERNAL MEMORY no direct access† CCR0 The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width. 7 0 LOC1 Bit Number 7:6 LOC0 IRC1 IRC0 ALE Bit Mnemonic LOC1:0 WR BW0 PD Function Lock Bits These two bits control read and write access to the OTPROM during normal operation.
8XC196MC, MD, MH USER’S MANUAL no direct access† CCR0 (Continued) The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width. 7 0 LOC1 Bit Number 3 2 1 LOC0 IRC1 IRC0 ALE Bit Mnemonic WR BW0 PD Function ALE Address Valid Strobe and Write Strobe WR These bits define which bus-control signals will be generated during external read and write cycles.
INTERFACING WITH EXTERNAL MEMORY no direct access† CCR1 The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. 7 0 1 1 Bit Number Bit Mnemonic 0 1 WDE BW1 IRC2 0 Function 7:6 1 To guarantee proper operation, write ones to these bits. 5 0 To guarantee proper operation, write zero to this bit. 4 1 To guarantee proper operation, write one to this bit.
8XC196MC, MD, MH USER’S MANUAL no direct access† CCR1 (Continued) The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. 7 0 1 1 Bit Number Bit Mnemonic 1 IRC2 0 1 WDE BW1 IRC2 0 Function Ready Control This bit, along with IRC0 (CCR0.4), IRC1 (CCR0.5), and the READY pin determine the number of wait states that can be inserted into the bus cycle.
INTERFACING WITH EXTERNAL MEMORY Bus Control 16-bit Multiplexed Address/Data AD15:0 (Ports 4 and 3) Bus Control 8-bit Address High AD15:8 (Port 4) 8-bit Multiplexed Address/Data AD7:0 (Port 3) 8XC196 8XC196 16-bit Bus 8-bit Bus A3068-01 Figure 15-3. Multiplexing and Bus Width Options After reset, but before the CCB fetch, the microcontroller is configured for 8-bit bus mode, regardless of the BUSWIDTH input.
8XC196MC, MD, MH USER’S MANUAL TXTAL1 XTAL1 CLKOUT † ALE TCLGX (min) BUSWIDTH Valid TAVGV AD15:0 Data In Address Out † The CLKOUT pin is available only on the 8XC196MC, MD. A3162-01 Figure 15-4. BUSWIDTH Timing Diagram (8XC196MC, MD) TXTAL1 XTAL1 ALE TAVGV BUSWIDTH TLLGV (max) TLLGX (min) AD15:0 Address Out Data In A3169-01 Figure 15-5.
INTERFACING WITH EXTERNAL MEMORY . Table 15-4. BUSWIDTH Signal Timing Definitions Symbol TAVGV Definition Address Valid to BUSWIDTH Setup Maximum time the external device has to assert or deassert BUSWIDTH after the microcontroller outputs the address. TCLGX† BUSWIDTH Hold after CLKOUT Low Minimum time the level of the BUSWIDTH signal must be valid after CLKOUT falls. TLLGV†† ALE Low to BUSWIDTH Setup Maximum time the external device has to assert or deassert BUSWIDTH after ALE falls.
8XC196MC, MD, MH USER’S MANUAL 15.3.2 16-bit Bus Timings When the microcontroller is configured to operate in the 16-bit bus-width mode, lines AD15:0 form a 16-bit multiplexed address/data bus. Figure 15-6 shows an idealized timing diagram for the external read and write cycles. Comprehensive timing specifications are shown in Figure 15-22 on page 15-32. The rising edge of the address latch enable (ALE) signal indicates that the microcontroller is driving an address onto the bus (AD15:0).
INTERFACING WITH EXTERNAL MEMORY XTAL1 CLKOUT † ALE Valid BUSWIDTH AD15:0 (read) Address Out Data In RD# INST AD15:0 (write) Valid Address Out Data Out WR# † The CLKOUT pin is available only on the 8XC196MC, MD. A3163-01 Figure 15-6.
8XC196MC, MD, MH USER’S MANUAL 15.3.3 8-bit Bus Timings When the microcontroller is configured to operate in the 8-bit bus mode, lines AD7:0 form a multiplexed lower address and data bus. Lines AD15:8 are not multiplexed; the upper address is latched and remains valid throughout the bus cycle. Figure 15-7 shows an idealized timing diagram for the external read and write cycles. One cycle is required for an 8-bit read or write. A 16bit access requires two cycles.
INTERFACING WITH EXTERNAL MEMORY XTAL1 CLKOUT † ALE BUSWIDTH AD15:8 AD7:0 (read) Address Out Address Out Address Out Low data in Address +1 Out High data in RD# INST AD7:0 (write) Address Out Low data out Address +1 Out High data out WR# † The CLKOUT pin is available only on the 8XC196MC, MD. A3164-01 Figure 15-7. Timings for 8-bit Buses 15.4 WAIT STATES (READY CONTROL) An external device can use the READY input to lengthen an external bus cycle.
8XC196MC, MD, MH USER’S MANUAL After the CCB1 fetch, the internal ready control circuitry allows slow external memory devices to increase the length of the read and write bus cycles. If the external memory device is not ready for access, it pulls the READY signal low and holds it low until it is ready to complete the operation, at which time it releases READY. While READY is low, the bus controller inserts wait states into the bus cycle. The internal ready control bits, CCR0.5, CCR0.4, and CCR1.
INTERFACING WITH EXTERNAL MEMORY CLKOUT † TCLYX (max) ALE TCLYX (min) READY TAVYV RD# AD15:0 (read) Address Out Data WR# AD15:0 (write) Address Out Data Out Address † The CLKOUT pin is available only on the 8XC196MC, MD. A3165-01 Figure 15-8.
8XC196MC, MD, MH USER’S MANUAL TXTAL1 XTAL1 TLHLH + 2TXTAL1 ALE TLLYX (max) TLLYX (min) TLLYV READY 16 MHz 8 MHz TAVYV TRLRH + 2TXTAL1 RD# TRLDV + 2TXTAL1 TAVDV + 2TXTAL1 AD15:0 (read) Address Out Data In TWLWH + 2TXTAL1 WR# TRLDV + 2TXTAL1 TQVWH + 2TXTAL1 AD15:0 (write) Address Out Data Out Address A3167-01 Figure 15-9. READY Timing Diagram — One Wait State (8XC196MH) Table 15-5.
INTERFACING WITH EXTERNAL MEMORY Table 15-5. READY Signal Timing Definitions (Continued) Symbol TLLYX†† Definition READY Hold after ALE Low Minimum time the level of the READY signal must be valid after ALE falls. If the maximum value is exceeded, additional wait states will occur. TLLYV†† ALE Low to READY Setup Maximum time the external device has to deassert READY after ALE falls. TQVWH Data Valid to WR# High Time between data being valid on the bus and the microcontroller deasserting WR#.
8XC196MC, MD, MH USER’S MANUAL 15.5.1 Standard Bus-control Mode In the standard bus-control mode, the microcontroller generates the standard bus-control signals: ALE, RD#, WR#, and BHE# (see Figure 15-10). ALE is asserted while the address is driven, and it can be used to latch the address externally. RD# is asserted for every external memory read, and WR# is asserted for every external memory write. When asserted, BHE# selects the bank of memory that is addressed by the high byte of the data bus.
INTERFACING WITH EXTERNAL MEMORY Figure 15-12 shows an 8-bit system with both flash and RAM. The flash is the lower half of memory, and the RAM is the upper half. This system configuration uses the most-significant address bit (AD15) as the chip-select signal and ALE as the address-latch signal. CS# CS# AD15 AD14:8 8XC196 AD7:0 74AC 373 A7:0 A14:8 D7:0 32K×8 Flash (28F256) A12:8 D7:0 A7:0 A7:0 8K×8 RAM LE ALE OE# OE# WE# RD# WR# A3140-01 Figure 15-12.
8XC196MC, MD, MH USER’S MANUAL Figure 15-13 shows a system that uses the dynamic bus-width feature. (The CCR bits, BW0 and BW1, are set.) Code is executed from the two EPROMs and data is stored in the byte-wide RAM. The RAM is in high memory. It is selected by driving AD15 high, which also selects the 8-bit bus-width mode by driving the BUSWIDTH signal low.
INTERFACING WITH EXTERNAL MEMORY 15.5.2 Write Strobe Mode The write strobe mode eliminates the need to externally decode high- and low-byte writes to an external 16-bit RAM or flash device in 16-bit bus mode. When the write strobe mode is selected, the microcontroller generates WRL# and WRH# instead of WR# and BHE#. WRL# is asserted for all low byte writes (even addresses) and all word writes. WRH# is asserted for all high byte writes (odd addresses) and all word writes.
8XC196MC, MD, MH USER’S MANUAL Figure 15-15 shows a 16-bit system with two EPROMs and two RAMs. It is configured to use the write strobe mode. ALE latches the address; AD15 is the chip-select signal for the memory devices. WRL# is asserted during low byte writes and word writes. WRH# is asserted during high byte writes and word writes. Note that the RAM devices do not use AD0. WRL# and WRH# determine whether the low byte (AD0=0) or high byte (AD0=1) is selected.
INTERFACING WITH EXTERNAL MEMORY 15.5.3 Address Valid Strobe Mode When the address valid strobe mode is selected, the microcontroller generates the address valid signal (ADV#) instead of the address latch enable signal (ALE). ADV# is asserted after an external address is valid (see Figure 15-16). This signal can be used to latch the valid address and simultaneously enable an external memory device. (See the examples in Figures 15-18 and 15-19.
8XC196MC, MD, MH USER’S MANUAL Figure 15-18 and Figure 15-19 show sample circuits that use the address valid strobe mode. Figure 15-18 shows a simple 8-bit system with a single flash. It is configured for the address valid strobe mode. This system configuration uses the ADV# signal as both the flash chip-select signal and the address-latch signal. RD# OE# A14:8 AD14:8 D7:0 32K×8 Flash (28F256) 8XC196 AD7:0 74AC 373 A7:0 A7:0 LE CS# ADV# A3094-01 Figure 15-18.
INTERFACING WITH EXTERNAL MEMORY Figure 15-19 shows a 16-bit system with two EPROMs. This system configuration uses the ADV# signal as both the EPROM chip-select signal and the address-latch signal. VCC BUSWIDTH AD15:8 CS# 74AC 373 A14:8 CS# A15:8 A13:7 A13:7 LE D15:8 ADV# D7:0 8XC196 AD7:0 LE 74AC 373 16K×8 EPROM (Low) 16K×8 EPROM (High) A7:1 A7:1 A6:0 A6:0 OE# OE# RD# A3095-01 Figure 15-19.
8XC196MC, MD, MH USER’S MANUAL 15.5.4 Address Valid with Write Strobe Mode When the address valid with write strobe mode is selected, the microcontroller generates the ADV#, RD#, WRL#, and WRH# bus-control signals. This mode is used for a simple system using an external 16-bit data bus. Figure 15-20 shows the timing. The RD# signal (not shown) is similar to WRL# and WRH#. The example system of Figure 15-21 uses address valid with write strobe to access byte-wide RAMs with a 16-bit data bus.
INTERFACING WITH EXTERNAL MEMORY VCC BUSWIDTH AD15:8 CS# 74AC 373 A13:8 A12:7 CS# A12:7 LE D15:8 ADV# D7:0 8XC196 AD7:0 8K×8 RAM (High) LE 74AC 373 8K×8 RAM (Low) A7:1 A6:0 A6:0 WE# WE# WRH# WRL# A3097-01 Figure 15-21. 16-bit System with RAM 15.6 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest datasheet for the AC timings to make sure your system meets specifications. The major external bus timing specifications are shown in Figure 15-22.
8XC196MC, MD, MH USER’S MANUAL TXTAL1 XTAL1 TCLCL TCHCL TXHCH CLKOUT † TCLLH TLLCH TLHLH ALE/ADV# TLHLL TLLRL TRLRH TRHLH RD# AD15:0 (read) TLLAX Address Out TAVDV TRHDZ TRLAZ TAVLL TRLDV Data In TLLWL TWLWH TWHLH WR# TQVWH AD15:0 (write) Address Out Data Out TWHQX Address Out TWHBX, TRHBX BHE#, INST Valid TWHAX, TRHAX AD15:8 (8-bit mode) Address Out † The CLKOUT pin is available only on the 8XC196MC, MD. A3166-01 Figure 15-22.
INTERFACING WITH EXTERNAL MEMORY 15.6.1 Explanation of AC Symbols Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. For example, TLLRL is the time between signal L (ALE/ADV#) condition L (Low), and signal R (RD#) condition L (Low). Table 15-7 defines the signal and condition codes. Table 15-7.
8XC196MC, MD, MH USER’S MANUAL Table 15-9. Microcontroller Meets These Specifications Symbol TAVLL Definition Address Setup to ALE/ADV# Low Length of time address is valid before ALE/ADV# falls. Useful when using an external latch to demultiplex the address from the address data bus. TCHCL† CLKOUT High CLKOUT Low CLKOUT pulse width. Useful when using CLKOUT to clock external devices. TCLCL† CLKOUT Cycle Time The period of the CLKOUT signal; equal to 2TXTAL1.
INTERFACING WITH EXTERNAL MEMORY Table 15-9. Microcontroller Meets These Specifications (Continued) Symbol TWHAX Definition Address (high byte) Hold after WR# High Minimum time the high byte of the address (when using an 8-bit data bus) is valid after the microcontroller deasserts WR#. TWHBX BHE#, INST Hold after WR# High Minimum time these signals are valid after the microcontroller deasserts WR#. TWHLH WR# High to ALE High Time between the microcontroller deasserting WR# and next ALE pulse.
16 Programming the Nonvolatile Memory
CHAPTER 16 PROGRAMMING THE NONVOLATILE MEMORY The 87C196MC and 87C196MD contain 16 Kbytes of one-time-programmable read-only memory (OTPROM); the 87C196MH contains 32 Kbytes. OTPROM is similar to EPROM, but it comes in an unwindowed package and cannot be erased. You can either program the OTPROM yourself or have the factory program it as a quick-turn ROM product (this option may not be available for all devices). This chapter provides procedures and guidelines to help you program the device.
8XC196MC, MD, MH USER’S MANUAL mode, you can program and verify single or multiple words in the OTPROM. This mode allows you to read the signature word and programming voltages and to program the PCCBs and unerasable PROM (UPROM) bits. Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer’s code and data.
PROGRAMMING THE NONVOLATILE MEMORY Table 16-1.
8XC196MC, MD, MH USER’S MANUAL 16.3.1.1 Controlling Access to the OTPROM During Normal Operation During normal operation, the lock bits in CCB0 control read and write accesses to the OTPROM. Table 16-2 describes the options. You can program the CCBs using any of the programming methods. Table 16-2. Memory Protection for Normal Operating Mode Read Protect LOC1 (CCR0.7) Write Protect LOC0 (CCR0.6) 1 1 No protection. Run-time programming is permitted, and the entire OTPROM array can be read.
PROGRAMMING THE NONVOLATILE MEMORY These protection levels are provided by the PCCB0 lock bits, the CCB0 lock bits, and the internal security key (Table 16-3). When entering programming modes, the reset sequence loads the PCCBs into the chip configuration registers. It also loads CCB0 into internal RAM to provide an additional level of security.
8XC196MC, MD, MH USER’S MANUAL You can program the internal security key in either auto or slave programming mode. Once the security key is programmed, you must provide a matching key to gain access to any programming mode. For auto programming and ROM-dump modes, a matching security key must reside in external memory. For slave programming mode, you must “program” a matching security key into the appropriate OTPROM locations with the program word command.
PROGRAMMING THE NONVOLATILE MEMORY Address: Reset State (MC, MD): Reset State (MH): USFR 1FF6H 02H XXH The unerasable PROM (USFR) register contains two bits that disable external fetches of data and instructions and another that detects a failed oscillator. These bits can be programmed, but cannot be erased. WARNING: These bits can be programmed, but can never be erased. Programming these bits makes dynamic failure analysis impossible.
8XC196MC, MD, MH USER’S MANUAL 16.4 PROGRAMMING PULSE WIDTH The programming pulse width is controlled in different ways, depending on the programming mode. In slave programming mode, the pulse width is controlled by the PALE# signal. In auto programming mode, it is loaded from the external EPROM into the PPW register. In the UPROM (8XC196MH only) and PCCB programming modes, the pulse width is controlled by the testROM routine. (For run-time programming, your software controls the pulse width.
PROGRAMMING THE NONVOLATILE MEMORY Table 16-5. Example PPW_VALUE Calculations FXTAL1 8XC196MC, MD (Two 250-µs pulses required) 8XC196MH (Five 100-µs pulses required) 8 MHz PPW_VALUE = 62.5 × 8 = 504 = 01F4H PPW_VALUE = 25 × 8 = 200 = 00C8H 16 MHz PPW_VALUE = 62.5 × 16 = 1000 = 03F8H PPW_VALUE = 25 × 16 = 400 = 0190H 16.5 MODIFIED QUICK-PULSE ALGORITHM Both the slave and auto programming routines use the modified quick-pulse algorithm (Figure 16-3).
8XC196MC, MD, MH USER’S MANUAL From Auto or Slave Programming Start PPW Timer Write Data to OTPROM Enable Interrupts Enter Idle Mode Wait for PPW Timer Interrupt No Required Writes Done ? Yes Compare Programmed Locations and Set Flags Return A0190-03 Figure 16-3. Modified Quick-pulse Algorithm Auto programming repeats the pulse twice (for the 87C196MC, MD) or five times (for the 87C196MH), using the pulse width you specify in the external EPROM.
PROGRAMMING THE NONVOLATILE MEMORY 16.6 PROGRAMMING MODE PINS Figure 16-4 illustrates the signals used in programming and Table 16-6 describes them. The EA#, VPP, and PMODE pins combine to control entry into programming modes. You must configure the PMODE (P0.7:4) pins to select the desired programming mode (see Table 16-7 on page 16-13). Each programming routine configures the port 2 pins to operate as the appropriate special-function signals.
8XC196MC, MD, MH USER’S MANUAL Table 16-6. Pin Descriptions (Continued) Port Pin P2.2 Specialfunction Signal PROG# Type Programming Mode I Slave Description Programming During programming, a falling edge latches data on the PBUS and begins programming, while a rising edge ends programming. The current location is programmed with the same data as long as PROG# remains asserted, so the data on the PBUS must remain stable while PROG# is active.
PROGRAMMING THE NONVOLATILE MEMORY Table 16-6. Pin Descriptions (Continued) Port Pin — Specialfunction Signal EA# Type Programming Mode I All Description External Access Controls program mode entry. If EA# is at VPP voltage on the rising edge of RESET#, the device enters programming mode. EA# is sampled and latched only on the rising edge of RESET#. Changing the level of EA# after reset has no effect. — VPP I All Programming Voltage During programming, the V PP pin is typically at +12.
8XC196MC, MD, MH USER’S MANUAL 16.7.2 Power-up and Power-down Sequences When you are ready to begin programming, follow these power-up and power-down procedures. WARNING Failure to observe these warnings will cause permanent device damage. • Voltage must not be applied to VPP while VCC is low. • The VPP voltage must be within 1 volt of VCC while VCC is less than 4.5 volts. VPP must not go above 4.5 volts until VCC is at least 4.5 volts. • • • • The VPP maximum voltage must not be exceeded.
PROGRAMMING THE NONVOLATILE MEMORY 16.8 SLAVE PROGRAMMING MODE Slave programming mode allows you to program and verify the entire OTPROM array, including the PCCBs and UPROM bits, by using an EPROM programmer. In this mode, ports 3 and 4 serve as the PBUS, transferring commands, addresses, and data. The least-significant bit of the PBUS (P3.0) controls the command (1 = program word; 0 = dump word) and the remaining 15 bits contain the address of the word to be programmed or dumped.
8XC196MC, MD, MH USER’S MANUAL Table 16-8. Device Signature Word and Programming Voltages Signature Word Programming VCC Programming V PP Location Location Device Location Value Value Value 8XC196MC, MD 0070H 8794H 0072H 40H 0073H 0A0H 8XC196MH 0070H 87DEH 0072H 40H 0073H 0A0H 16.8.2 Slave Programming Circuit and Memory Map Figure 16-5 shows the circuit diagram and Table 16-9 shows the memory map for slave programming mode.
PROGRAMMING THE NONVOLATILE MEMORY Table 16-9. Slave Programming Mode Memory Map Description OTPROM Address Comments (MH) 2000–9FFFH OTPROM Cells (MC, MD) 2000–5FFFH DED† 0758H UPROM Cell DEI† 0718H UPROM Cell PCCB Programming voltages (see Table 16-8 on page 16-16) Signature word 0218H Test EPROM 0072H, 0073H Read Only 0070H Read Only †These bits program the UPROM cells. Once these bits are programmed, they cannot be erased and dynamic failure analysis of the device is impossible. 16.8.
8XC196MC, MD, MH USER’S MANUAL no direct access CCR1, CCR0 The chip configuration registers (CCRs) control wait states, powerdown mode, and internal memory protection. These registers are loaded from the PCCBs during programming modes and from the CCBs for normal operation. 7 0 1 1 0 1 WDE BW1 IRC2 0 LOC1 LOC0 IRC1 IRC0 ALE WR BW0 PD 7 0 Bit Mnemonic Function WDE Watchdog Timer Enable BW1 Buswidth Control PCCB default is initially disabled (enabled the first time WDT is cleared).
PROGRAMMING THE NONVOLATILE MEMORY 16.8.4 Slave Programming Routines The slave programming mode algorithm consists of three routines: the address/command decoding routine, the program word routine, and the dump word routine. The address/command decoding routine (Figure 16-7) reads the PBUS and transfers control to the program word or dump word routine based on the value of P3.0. A one on P3.0 selects the program word command and the remaining bits specify the address.
8XC196MC, MD, MH USER’S MANUAL Other Modes No PMODE = 05H ? Yes No PALE# (P2.1) = 0 ? Yes Read Data From PBUS Deassert CPVER Assert PVER No PVER (P2.0) = 1 ? Yes PALE# (P2.1)= 0 ? Yes No Check Address Dump Word Routine No P3.0 = 1 ? Yes Program Word Routine A0193-02 Figure 16-7.
PROGRAMMING THE NONVOLATILE MEMORY From Address/ Command Decoder No PROG# (P2.2)=0 ? Yes Lock Bits Enabled ? Read Data from PBUS Yes Verify Security Key No Execute Modified Yes Quick-Pulse Algorithm then Return Programming Verifies ? Read Data from PBUS No Keys Match ? No Loop Forever Deassert PVER (P2.0 = 0) Yes Assert PVER (P2.0 = 1) Yes PROG# (P2.2) = 0 ? No To Address/ Command Decoder Yes PALE# (P2.1) = 0 ? No AINC# (P2.4) = 0 ? Yes Increment Address by 2 No PVER (P2.
8XC196MC, MD, MH USER’S MANUAL Figure 16-9 shows the timings of the program word command with a repeated programming pulse and auto increment. Asserting PALE# latches the command and address on the PBUS. Asserting PROG# latches the data on the PBUS and starts the programming sequence. The PROG# signal controls the programming pulse width. (Slave programming mode does not use the PPW register.
PROGRAMMING THE NONVOLATILE MEMORY From Address/ Command Decoder Yes Lock Bits Enabled ? No Get Data from OPTROM PROG# (P2.2) = 0 ? No Yes Write Data to PBUS No PROG# (P2.2) = 1 ? Yes Write 0FFFFH to PBUS To Address/ Command Decoder Yes PALE# (P2.1) = 0 ? No AINC# (P2.4) = 0 ? Yes No Increment Address by 2 A0189-03 Figure 16-10.
8XC196MC, MD, MH USER’S MANUAL Figure 16-11 shows the timings of the dump word command. PROG# governs when the device drives the bus. The timings before the dump word command are the same as those shown in Figure 16-9. In the dump word mode, the AINC# pin can remain active and toggling. The PROG# pin automatically increments the address. RESET# TSHLL ADDR1 PBUS (Ports 3/4) ADDR2 Word Dump ADDR/COMMAND TPLDV TPHDX Word Dump TPLDV TPHDX PALE# PROG# TILPL TPHPL AINC# A0122-02 Figure 16-11.
PROGRAMMING THE NONVOLATILE MEMORY Table 16-10. Timing Mnemonics (Continued) Mnemonic Description TPHPL PROG# High to Next PROG# Low. TPHIL PROG# High to AINC# Low. TILIH AINC# Pulse Width. TILVH PVER Hold After AINC# Low. TILPL AINC# Low to PROG# Low. TPHVL PROG# High to PVER Valid. 16.9 AUTO PROGRAMMING MODE The auto programming mode is a low-cost programming alternative.
8XC196MC, MD, MH USER’S MANUAL VCC 20 pF 20 pF 100 kΩ XTAL1 XTAL2 Reset RESET# VCC +5.0V 1.0µF VSS VCC READY/P5.6 NMI BUSWIDTH/P5.7 1 kΩ 74HC14 10µF EA# VPP +12.50V VCC VREF P0.7/ PMODE.3 P0.6/ PMODE.2 VCC RD#/P5.3 P0.5/ PMODE.1 MH P1.3:0 AD11:8 P0.4/ PMODE.0 MC/MD AD15:8 OE# CE# A15:8 ANGND 270kΩ ALE/P5.0 LE OE# 27(C)512 AD7:0 74LS373 74HC14 ON = Programming VCC A7:0 O7:0 P2.7/PACT# P2.5 P2.4 P2.3 P2.2 P2.1 270kΩ P2.
PROGRAMMING THE NONVOLATILE MEMORY Table 16-11. 8XC196MC/MD Auto Programming Memory Map Address Output from 8XC196MC, 8XC196MD 4014H Internal OTPROM Address Address Using Circuit in Figure 16-12 (A15:0) N/A 14H Description Programming pulse width (PPW) LSB. 4015H N/A 15H 4020–402FH 2020–202FH 0020–002FH Security key for verification. Programming pulse width (PPW) MSB. 4000–7FFFH 2000–5FFFH 4000–7FFFH Code, data, and reserved locations. Table 16-12.
8XC196MC, MD, MH USER’S MANUAL Other Modes No Yes PMODE = 0CH ? No Lock Bits Enabled ? Yes Verify Security Key No Pass ? Loop Forever Yes Assert PACT# Load PPW Get External Data Yes Data = 0FFFFH ? No Execute Modified Quick-Pulse Algorithm then Return Error Programming ? No Yes Clear PVER Increment Address Pointer No Top of OTPROM ? Yes Deassert PACT# Loop Forever (Done) A0191-03 Figure 16-13.
PROGRAMMING THE NONVOLATILE MEMORY If the security key verification is successful, the routine loads the programming pulse width (PPW) value from the external EPROM into the internal PPW register. It then asserts PACT#, indicating that programming has begun. (PACT# is also active during reset, although no programming is in progress.) PVER is initially asserted and remains asserted unless an error is detected, in which case it is deasserted.
8XC196MC, MD, MH USER’S MANUAL 2. Using another blank EPROM device, follow these steps to program only CCB0. — Place the programming pulse width (PPW) in external locations 14H–15H. — Place the appropriate CCB0 value in external location 4018H. — Place the security key to be verified in external EPROM locations 0020H–002FH. This value must match the security key programmed in step 1. — Leave the remaining EPROM locations unprogrammed (0FFFFH).
PROGRAMMING THE NONVOLATILE MEMORY Figure 16-14 shows the recommended circuit for PCCB and UPROM programming. In these circuits, the PBUS holds data to be written to the OTPROM, PALE# begins programming, and PVER drives an LED that lights to indicate successful programming. VCC 20 pF 20 pF 100 kΩ XTAL1 XTAL2 Reset RESET# VCC +5.0V 1.0µF VCC READY/P5.6 VSS NMI BUSWIDTH/P5.7 EA# 1 kΩ 74HC14 10µF VPP +12.50V VCC VCC 10kΩ VREF SW1 Pullups Required P4.7 – P3.0 P0.7 P0.6 P0.5 P4.7:0 P0.4 P0.
8XC196MC, MD, MH USER’S MANUAL Table 16-13. PCCB and UPROM Programming Values Pins PCCB Programming UPROM Programming PMODE3:0 0DH 09H P4.7:0 FFH FFH P3.7:0 Data to be programmed in PCCB (See CCR descriptions in Appendix C) Value to program UPROM bits: 04H to program DED only 08H to program DEI only 0CH to program both DED and DEI Assert PALE# to begin programming.
PROGRAMMING THE NONVOLATILE MEMORY The calling routine must pass two parameters to this routine — the data to be programmed (in DATA_TEMP) and the address (in ADDR_TEMP).
A Instruction Set Reference
APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS® 96 microcontrollers. It defines the processor status word (PSW) flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes, instruction lengths, and execution times. It includes the following tables. • Table A-1 on page A-2 is a map of the opcodes.
8XC196MC, MD, MH USER’S MANUAL Table A-1.
INSTRUCTION SET REFERENCE Table A-1.
8XC196MC, MD, MH USER’S MANUAL Table A-2. Processor Status Word (PSW) Flags Mnemonic C Description The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of the last bit shifted out of an operand. If a subtraction operation generates a borrow, the carry flag is cleared. C Value of Bits Shifted Off 0 < ½ LSB 1 ≥ ½ LSB Normally, the result is rounded up if the carry flag is set. The sticky bit flag allows a finer resolution in the rounding decision.
INSTRUCTION SET REFERENCE Table A-3 shows the effect of the PSW flags or a specified condition on conditional jump instructions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction on the PSW flags. Table A-3.
8XC196MC, MD, MH USER’S MANUAL Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands. Table A-5. Operand Variables Variable Description aa A 2-bit field within an opcode that selects the basic addressing mode used. This field is present only in those opcodes that allow addressing mode options. The field is encoded as follows: baop A byte operand that is addressed by any addressing mode.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set Mnemonic ADD (2 operands) Operation Instruction Format ADD WORDS. Adds the source and destination word operands and stores the sum into the destination operand. (DEST) ← (DEST) + (SRC) DEST, SRC ADD wreg, waop (011001aa) (waop) (wreg) PSW Flag Settings ADD (3 operands) Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — ADD WORDS. Adds the two source word operands and stores the sum into the destination operand.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic ADDCB Operation Instruction Format ADD BYTES WITH CARRY. Adds the source and destination byte operands and the carry flag (0 or 1) and stores the sum into the destination operand. DEST, SRC ADDCB breg, baop (101101aa) (baop) (breg) (DEST) ← (DEST) + (SRC) + C PSW Flag Settings AND (2 operands) Z N C V VT ST ↓ ✓ ✓ ✓ ↑ — LOGICAL AND WORDS.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ANDB (3 operands) LOGICAL AND BYTES. ANDs the two source byte operands and stores the result into the destination operand. The result has ones in only the bit positions in which both operands had a “1” and zeros in all other bit positions.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic BMOVI Operation Instruction Format INTERRUPTIBLE BLOCK MOVE. Moves a block of word data from one location in memory to another. The instruction is identical to BMOV, except that BMOVI is interruptible. The source and destination addresses are calculated using the indirect with autoincrement addressing mode. A long register (PTRS) addresses the source and destination pointers, which are stored in adjacent word registers.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic CLRB Operation Instruction Format CLEAR BYTE. Clears the value of the operand. (DEST) ← 0 DEST CLRB breg (00010001) (breg) PSW Flag Settings CLRC Z N C V VT ST 1 0 0 0 — — CLEAR CARRY FLAG. Clears the carry flag. C←0 CLRC (11111000) PSW Flag Settings CLRVT Z N C V VT ST — — 0 — — — CLEAR OVERFLOW-TRAP FLAG. Clears the overflow-trap flag.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic CMPL Operation Instruction Format COMPARE LONG. Compares the magnitudes of two double-word (long) operands. The operands are specified using the direct addressing mode. The flags are altered, but the operands remain unaffected. If a borrow occurs, the carry flag is cleared; otherwise, it is set.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic DIV Operation Instruction Format DIVIDE INTEGERS. Divides the contents of the destination long-integer operand by the contents of the source integer word operand, using signed arithmetic. It stores the quotient into the low-order word of the destination (i.e., the word with the lower address) and the remainder into the high-order word. The following two statements are performed concurrently.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic DIVUB Operation Instruction Format DIVIDE BYTES, UNSIGNED. This instruction divides the contents of the destination word operand by the contents of the source byte operand, using unsigned arithmetic. It stores the quotient into the low-order byte (i.e., the byte with the lower address) of the destination operand and the remainder into the high-order byte. The following two statements are performed concurrently.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic DPTS Operation Instruction Format DISABLE PERIPHERAL TRANSACTION SERVER (PTS). Disables the peripheral transaction server (PTS). PTS Disable (PSW.2) ←0 DPTS (11101100) PSW Flag Settings EI Z N C V VT ST — — — — — — ENABLE INTERRUPTS. Enables interrupts following the execution of the next statement. Interrupt calls cannot occur immediately following this instruction. EI (11111011) Interrupt Enable (PSW.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic EXTB Operation Instruction Format SIGN-EXTEND SHORT-INTEGER INTO INTEGER. Sign-extends the low-order byte of the operand throughout the high-order byte of the operand. if DEST.7 = 1 then (high byte DEST) else (high byte DEST) end_if EXTB wreg (00010110) (wreg) ← 0FFH ←0 PSW Flag Settings IDLPD Z N C V VT ST ✓ ✓ 0 0 — — IDLE/POWERDOWN.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic INCB Operation Instruction Format INCREMENT BYTE. Increments the value of the byte operand by 1. (DEST) ← (DEST) + 1 INCB breg (00010111) (breg) PSW Flag Settings JBC Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — JUMP IF BIT IS CLEAR. Tests the specified bit. If the bit is set, control passes to the next sequential instruction.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic JC Operation Instruction Format JUMP IF CARRY FLAG IS SET. Tests the carry flag. If the carry flag is clear, control passes to the next sequential instruction. If the carry flag is set, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in the range of –128 to +127.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic JGT Operation Instruction Format JUMP IF SIGNED GREATER THAN. Tests both the zero flag and the negative flag. If either flag is set, control passes to the next sequential instruction. If both flags are clear, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in the range of –128 to +127.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic JLT Operation Instruction Format JUMP IF SIGNED LESS THAN. Tests the negative flag. If the flag is clear, control passes to the next sequential instruction. If the negative flag is set, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in the range of –128 to +127.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic JNH Operation Instruction Format JUMP IF NOT HIGHER (UNSIGNED). Tests both the zero flag and the carry flag. If the carry flag is set and the zero flag is clear, control passes to the next sequential instruction. If either the carry flag is clear or the zero flag is set, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic JNVT Operation Instruction Format JUMP IF OVERFLOW-TRAP FLAG IS CLEAR. Tests the overflow-trap flag. If the flag is set, this instruction clears the flag and passes control to the next sequential instruction. If the overflow-trap flag is clear, this instruction adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in range of –128 to +127.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic JVT Operation Instruction Format JUMP IF OVERFLOW-TRAP FLAG IS SET. Tests the overflow-trap flag. If the flag is clear, control passes to the next sequential instruction. If the overflow-trap flag is set, this instruction clears the flag and adds to the program counter the offset between the end of this instruction and the target label, effecting the jump. The offset must be in range of –128 to +127.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic LDBSE Operation Instruction Format LOAD BYTE SIGN-EXTENDED. Signextends the value of the source shortinteger operand and loads it into the destination integer operand. (low byte DEST) DEST, SRC LDBSE wreg, baop (101111aa) (baop) (wreg) ← (SRC) if DEST.15 = 1 then (high word DEST) ← 0FFH else (high word DEST) ← 0 end_if PSW Flag Settings LDBZE Z N C V VT ST — — — — — — LOAD BYTE ZERO-EXTENDED.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MUL (2 operands) MULTIPLY INTEGERS. Multiplies the source and destination integer operands, using signed arithmetic, and stores the 32-bit result into the destination long-integer operand. The sticky bit flag is undefined after the instruction is executed.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULU (2 operands) MULTIPLY WORDS, UNSIGNED. Multiplies the source and destination word operands, using unsigned arithmetic, and stores the 32bit result into the destination double-word operand. The sticky bit flag is undefined after the instruction is executed.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic NEG Operation Instruction Format NEGATE INTEGER. Negates the value of the integer operand. (DEST) ← – (DEST) NEG wreg (00000011) (wreg) PSW Flag Settings NEGB Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — NEGATE SHORT-INTEGER. Negates the value of the short-integer operand. (DEST) ← – (DEST) NEGB breg (00010011) (breg) PSW Flag Settings NOP Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — NO OPERATION. Does nothing.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic NOT Operation Instruction Format COMPLEMENT WORD. Complements the value of the word operand (replaces each “1” with a “0” and each “0” with a “1”). (DEST) ← NOT (DEST) NOT wreg (00000010) (wreg) PSW Flag Settings NOTB Z N C V VT ST ✓ ✓ 0 0 — — COMPLEMENT BYTE. Complements the value of the byte operand (replaces each “1” with a “0” and each “0” with a “1”).
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic POP Operation Instruction Format POP WORD. Pops the word on top of the stack and places it at the destination operand. (DEST) ← (SP) SP ← SP + 2 POP waop (110011aa) (waop) PSW Flag Settings POPA Z N C V VT ST — — — — — — POP ALL. This instruction is used instead of POPF, to support the eight additional interrupts.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic PUSHA Operation Instruction Format PUSH ALL. This instruction is used instead of PUSHF, to support the eight additional interrupts. It pushes two words — PSW/INT_MASK and INT_MASK1/WSR — onto the stack. PUSHA (11110100) This instruction clears the PSW, INT_MASK, and INT_MASK1 registers and decrements the SP by 4. Interrupt calls cannot occur immediately following this instruction.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic RST Operation Instruction Format RESET SYSTEM. Initializes the PSW to zero, the PC to 2080H, and the pins and SFRs to their reset values. Executing this instruction causes the RESET# pin to be pulled low for 16 state times. RST (11111111) SFR ← Reset Status Pin ← Reset Status PSW ← 0 PC ← 2080H PSW Flag Settings SCALL Z N C V VT ST 0 0 0 0 0 0 SHORT CALL.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic SHL Operation Instruction Format SHIFT WORD LEFT. Shifts the destination word operand to the left as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. The right bits of the result are filled with zeros.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic SHLL Operation Instruction Format SHIFT DOUBLE-WORD LEFT. Shifts the destination double-word operand to the left as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. The right bits of the result are filled with zeros.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic SHRA Operation Instruction Format ARITHMETIC RIGHT SHIFT WORD. Shifts the destination word operand to the right as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. If the original high order bit value was “0,” zeros are shifted in.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic SHRAL Operation Instruction Format ARITHMETIC RIGHT SHIFT DOUBLEWORD. Shifts the destination double-word operand to the right as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic SHRL Operation Instruction Format LOGICAL RIGHT SHIFT DOUBLE-WORD. Shifts the destination double-word operand to the right as many times as specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any register (10H – 0FFH) with a value in the range of 0 to 31 (1FH), inclusive. The left bits of the result are filled with zeros.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic ST Operation Instruction Format STORE WORD. Stores the value of the source (leftmost) word operand into the destination (rightmost) operand. (DEST) ← (SRC) SRC, DEST ST wreg, waop (110000aa) (waop) (wreg) PSW Flag Settings STB Z N C V VT ST — — — — — — STORE BYTE. Stores the value of the source (leftmost) byte operand into the destination (rightmost) operand.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic SUBB (2 operands) Operation Instruction Format SUBTRACT BYTES. Subtracts the source byte operand from the destination byte operand, stores the result in the destination operand, and sets the carry flag as the complement of borrow. DEST, SRC SUBB breg, baop (011110aa) (baop) (breg) (DEST) ← (DEST) – (SRC) PSW Flag Settings SUBB (3 operands) Z N C V VT ST ✓ ✓ ✓ ✓ ↑ — SUBTRACT BYTES.
INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic TIJMP Operation Instruction Format TABLE INDIRECT JUMP. Causes execution to continue at an address selected from a table of addresses. The first word register, TBASE, contains the 16-bit address of the beginning of the jump table. TBASE can be located in RAM up to FEH without windowing or above FFH with windowing. The jump table itself can be placed at any nonreserved memory location on a word boundary.
8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic XCH Operation Instruction Format EXCHANGE WORD. Exchanges the value of the source word operand with that of the destination word operand. (DEST) ↔ (SRC) DEST, SRC XCH wreg, waop (00000100) (waop) (wreg) direct (00001011) (waop) (wreg) indexed PSW Flag Settings XCHB Z N C V VT ST — — — — — — EXCHANGE BYTE. Exchanges the value of the source byte operand with that of the destination byte operand.
INSTRUCTION SET REFERENCE Table A-7 lists the instruction opcodes, in hexadecimal order, along with the corresponding instruction mnemonics. Table A-7.
8XC196MC, MD, MH USER’S MANUAL Table A-7.
INSTRUCTION SET REFERENCE Table A-7.
8XC196MC, MD, MH USER’S MANUAL Table A-7.
INSTRUCTION SET REFERENCE Table A-7.
8XC196MC, MD, MH USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic F0 RET F2 PUSHF F3 POPF F4 PUSHA F5 POPA F6 IDLPD F7 TRAP F8 CLRC F9 SETC FA DI FB EI FC CLRVT FD NOP FE DIV/DIVB/MUL/MULB (Note 2) FF RST NOTES: 1. This opcode is reserved, but it does not generate an unimplemented opcode interrupt. 2. Signed multiplication and division are two-byte instructions.
INSTRUCTION SET REFERENCE Table A-8 lists instructions along with their lengths and opcodes for each applicable addressing mode. A dash (—) in any column indicates “not applicable.” Table A-8.
8XC196MC, MD, MH USER’S MANUAL Table A-8.
INSTRUCTION SET REFERENCE Table A-8.
8XC196MC, MD, MH USER’S MANUAL Table A-8.
INSTRUCTION SET REFERENCE Table A-8.
8XC196MC, MD, MH USER’S MANUAL Table A-9 lists instructions alphabetically within groups, along with their execution times, expressed in state times. Table A-9. Instruction Execution Times (in State Times) Arithmetic (Group I) Indirect Mnemonic Direct Immed. Normal Reg. Mem. Indexed Autoinc. Reg. Mem. Short Reg. Long Mem. Reg. Mem.
INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Arithmetic (Group II) Indirect Mnemonic Direct Immed. Normal Indexed Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
8XC196MC, MD, MH USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Stack (Register) Indirect Mnemonic Direct Immed. Normal Indexed Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Data Mnemonic Indirect BMOV register/register memory/register memory/memory 6 + 8 per word 6 + 11 per word 6 + 14 per word BMOVI register/register memory/register memory/memory 7 + 8 per word + 14 per interrupt 7 + 11 per word + 14 per interrupt 7 + 14 per word + 14 per interrupt Indirect Mnemonic Direct Immed. Normal Reg. Indexed Autoinc. Mem. Reg. Mem. Short Reg. Long Mem. Reg. Mem.
8XC196MC, MD, MH USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Call (Memory) Indirect Mnemonic LCALL Direct Indexed Immed. Normal Autoinc.
INSTRUCTION SET REFERENCE Table A-9.
B Signal Descriptions
APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196MC, 8XC196MD, and 8XC196MH. B.1 SIGNAL NAME CHANGES The names of some 8XC196MC and 8XC196MD signals have been changed for consistency with other MCS® 96 microcontrollers. Table B-1 lists the old and new names. Table B-1. Signal Name Changes Name in 8XC196MC User’s Manual B.
8XC196MC, MD, MH USER’S MANUAL Table B-2. 8XC196MC Signals Arranged by Functional Categories Address & Data AD15:0 Programming Control AINC# Bus Control & Status Input/Output P0.7:0/ACH7:0 CPVER P1.0/ACH8 P6.6/PWM0 PACT# P1.1/ACH9 P6.7/PWM1 ALE/ADV# PALE# P1.2/ACH10/T1CLK BHE#/WRH# PBUS.15:0 P1.3/ACH11/T1DIR BUSWIDTH PMODE.3:0 P1.4/ACH12 INST PROG# P2.3:0/EPA3:0 READY PVER RD# P2.6:4/COMP2:0 P2.7/COMP3 WR#/WRL# Processor Control CLKOUT Power & Ground P3.7:0 P4.7:0 EA# P5.
SIGNAL DESCRIPTIONS VSS 1 64 P5.6 / READY P5.0 / ALE / ADV# 2 63 P5.4 / ONCE# VPP 3 62 P5.3 / RD# 4 61 EXTINT VSS P5.5 / BHE# / WRH# 5 60 XTAL1 P5.2 / WR# / WRL# 6 59 XTAL2 P5.7 / BUSWIDTH 7 58 P6.6 / PWM0 AD14 / P4.6 / PBUS.14 8 57 P6.7 / PWM1 AD13 / P4.5 / PBUS.13 9 56 P2.6 / COMP2 / CPVER AD15 / P4.7 / PBUS.15 VCC 10 55 P2.5 / COMP1 / PACT# 11 54 P2.4 / COMP0 / AINC# AD12 / P4.4 / PBUS.12 12 53 P2.3 / EPA3 AD11 / P4.3 / PBUS.11 13 52 P2.
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 P5.7 / BUSWIDTH P5.2 / WR# / WRL# NC P5.5 / BHE# / WRH# P5.3 / RD# VPP P5.0 / ALE / ADV# VSS P5.1 / INST P5.6 / READY P5.4 / ONCE# EXTINT VSS XTAL1 XTAL2 NC NC NC P6.6 / PWM0 P6.7 / PWM1 P2.6 / COMP2 / CPVER 8XC196MC, MD, MH USER’S MANUAL 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 x8XC196MC View of component as mounted on PC board 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 P2.5 / COMP1 / PACT# P2.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P5.5 / BHE# / WRH# P5.3 / RD# VPP P5.0 / ALE / ADV# VSS P5.1 / INST P5.6 / READY P5.4 / ONCE# EXTINT VSS XTAL1 XTAL2 NC NC NC P6.6 / PWM0 SIGNAL DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 x8XC196MC View of component as mounted on PC board 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P6.7 / PWM1 P2.6 / COMP2 / CPVER P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# NC NC P2.7 / COMP3 P2.3 / EPA3 P2.
8XC196MC, MD, MH USER’S MANUAL Table B-3. 8XC196MD Signals Arranged by Functional Categories Address & Data AD15:0 Programming Control Input/Output Input/Output (Cont’d) AINC# P0.7:0/ACH7:0 P7.1:0/EPA5:4 CPVER P1.1:0/ACH9:8 P7.3:2/COMP5:4 PACT# P1.2/ACH10/T1CLK P7.6:4 ALE/ADV# PALE# P1.3/ACH11/T1DIR P7.7/FREQOUT BHE#/WRH# PBUS.15:0 P1.5:4/ACH13:12 BUSWIDTH PMODE.3:0 P1.7:6 INST PROG# P2.3:0/EPA3:0 READY PVER Bus Control & Status RD# WR#/WRL# P2.7:4/COMP3:0 P3.
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 P5.7 / BUSWIDTH P5.2 / WR# / WRL# NC P5.5 / BHE# / WRH# P5.3 / RD# VPP P5.0 / ALE / ADV# VSS P5.1 / INST P5.6 / READY P5.4 / ONCE# EXTINT VSS XTAL1 XTAL2 P7.6 P7.5 P7.4 P6.6 / PWM0 P6.7 / PWM1 P2.6 / COMP2 / CPVER SIGNAL DESCRIPTIONS 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 x8XC196MD View of component as mounted on PC board 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 P2.5 / COMP1 / PACT# P2.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P5.5 / BHE# / WRH# P5.3 / RD# VPP P5.0 / ALE / ADV# VSS P5.1 / INST P5.6 / READY P5.4 / ONCE# EXTINT VSS XTAL1 XTAL2 P7.6 P7.5 P7.4 P6.6 / PWM0 8XC196MC, MD, MH USER’S MANUAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 x8XC196MD View of component as mounted on PC board 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P6.7 / PWM1 P2.6 / COMP2 / CPVER P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# P7.3 / COMP5 P7.
SIGNAL DESCRIPTIONS Table B-4. 8XC196MH Signals Arranged by Functional Categories Address & Data AD15:0 Programming Control Input/Output AINC# P0.5:0/ACH5:0 Input/Output (Cont’d) P5.0 CPVER P0.6/ACH6/T1CLK P5.1 PACT# P0.7/ACH7/T1DIR P5.7:2 ALE/ADV# PALE# P1.0/TXD0 P6.0/WG1# BHE#/WRH# PBUS.15:0 P1.1/RXD0 P6.1/WG1 BUSWIDTH PMODE.3:0 P1.2/TXD1 P6.2/WG2# INST PROG# P1.3/RXD1 P6.3/WG2 READY PVER P2.0/EPA0 P6.4/WG3# Bus Control & Status RD# WR#/WRL# Power & Ground P2.
8XC196MC, MD, MH USER’S MANUAL VSS 1 64 P5.6 / READY P5.0 / ALE / ADV# VPP 2 63 P5.4 / ONCE# 3 62 P5.3 / RD# 4 61 EXTINT VSS P5.5 / BHE# / WRH# 5 60 XTAL1 P5.2 / WR# / WRL# 6 59 XTAL2 P5.7 / BUSWIDTH 7 58 P6.6 / PWM0 AD14 / P4.6 / PBUS.14 8 57 P2.7 / SCLK1# / BCLK1 AD13 / P4.5 / PBUS.13 9 56 P2.6 / COMP2 / CPVER AD15 / P4.7 / PBUS.15 10 55 P2.5 / COMP1 / PACT# VCC 11 54 P2.4 / COMP0 / AINC# AD12 / P4.4 / PBUS.12 12 53 P2.3 / COMP3 AD11 / P4.3 / PBUS.
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 P5.7 / BUSWIDTH P5.2 / WR# / WRL# NC P5.5 / BHE# / WRH# P5.3 / RD# VPP P5.0 / ALE / ADV# VSS P5.1 / INST P5.6 / READY P5.4 / ONCE# EXTINT VSS XTAL1 XTAL2 NC NC NC P6.6 / PWM0 P6.7 / PWM1 P2.6 / COMP2 / CPVER SIGNAL DESCRIPTIONS x8XC196MH View of component as mounted on PC board 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# NC NC P2.7 / SCLK1# / BCLK1 P2.3 / COMP3 P2.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P5.5 / BHE# / WRH# P5.3 / RD# VPP P5.0 / ALE / ADV# VSS P5.1 / INST P5.6 / READY P5.4 / ONCE# EXTINT VSS XTAL1 XTAL2 NC NC NC P6.6 / PWM0 8XC196MC, MD, MH USER’S MANUAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 x8XC196MH View of component as mounted on PC board 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P6.7 / PWM1 P2.6 / COMP2 / CPVER P2.5 / COMP1 / PACT# P2.4 / COMP0 / AINC# NC NC P2.
SIGNAL DESCRIPTIONS Table B-5. Description of Columns of Table B-6 Column Heading Description Name Lists the signals, arranged alphabetically. Many pins have two functions, so there are more entries in this column than there are pins. Every signal is listed in this column. Type Identifies the pin function listed in the Name column as an input (I), output (O), bidirectional (I/O), power (PWR), or ground (GND). Note that all inputs except RESET# are sampled inputs. RESET# is a levelsensitive input.
8XC196MC, MD, MH USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name AINC# Type I Description Auto Increment During slave programming, this active-low input enables the auto-increment feature. (Auto increment allows reading or writing of sequential OTPROM locations, without requiring address transactions across the PBUS for each read or write.) AINC# is sampled after each location is programmed or dumped.
SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name BUSWIDTH Type I Description Bus Width Two chip configuration register bits, CCR0.1 and CCR1.2, along with the BUSWIDTH pin, control the data bus width. When both CCR bits are set, the BUSWIDTH signal selects the external data bus width. When only one CCR bit is set, the bus width is fixed at either 16 or 8 bits, and the BUSWIDTH signal has no effect. CCR0.1 0 1 1 1 CCR1.
8XC196MC, MD, MH USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name EPA3:0 (MC) EPA5:0 (MD) EPA1:0 (MH) Type I/O Description Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. EPA5:0 are multiplexed as follows: EPA0/P2.0/PVER, EPA1/P2.1/PALE# (MC, MD), EPA1/P2.2/PROG# (MH), EPA2/P2.2/PROG#, EPA3/P2.3, EPA4/P7.0, and EPA5/P7.1. EPA5:4 are not implemented on the 8XC196MC and EPA5:2 are not implemented on the 8XC196MH.
SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name ONCE# Type I Description On-circuit Emulation Holding ONCE# low during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. This mode puts all pins, except XTAL1 and XTAL2, into a high-impedance state, thereby isolating the device from other components in the system. The value of ONCE# is latched when the RESET# pin goes inactive.
8XC196MC, MD, MH USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name P2.7:0 Type I/O Description Port 2 This is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. P2.6 is multiplexed with a special test-mode-entry function. If this pin is held low during reset, the device will enter a reserved test mode, so exercise caution if you use this pin for input.
SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name P7.7:0 (MD only) Type I/O Description Port 7 This is a standard, 8-bit, bidirectional port with Schmitt-trigger inputs. Port 7 is multiplexed as follows: P7.0/EPA4, P7.1/EPA5, P7.2/COMP4, P7.3/COMP5, and P7.7/FREQOUT. P7.6:4 are not multiplexed. Port 7 is not implemented on the 8XC196MC and 8XC196MH.
8XC196MC, MD, MH USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name PROG# Type I Description Programming Start During programming, a falling edge latches data on the PBUS and begins programming, while a rising edge ends programming. The current location is programmed with the same data as long as PROG# remains asserted, so the data on the PBUS must remain stable while PROG# is active.
SIGNAL DESCRIPTIONS Table B-6. Signal Descriptions (Continued) Name SCLK1:0# (MH only) Type I/O Description Shift Clock 0 and 1 In SIO mode 4, SCLKx# are bidirectional shift clock signals that synchronize the serial data transfer. The DIR bit in the SP_CON register controls the direction of SCLKx#. DIR = 1 allows an external shift clock to be input on SCLKx#. DIR = 0 causes SCLKx# to output the internal shift clock. SCLK0# is multiplexed with P2.1, BCLK0, and PALE#. SCLK1# is multiplexed with P2.
8XC196MC, MD, MH USER’S MANUAL Table B-6. Signal Descriptions (Continued) Name WG3:1 Type O Description Waveform Generator Phase 1–3 Positive Outputs 3-phase output signals used in motion-control applications. WG1 is multiplexed with P6.1, WG2 is multiplexed with P6.3, and WG3 is multiplexed with P6.5. WG3:1# O Waveform Generator Phase 1–3 Negative Outputs Complimentary 3-phase output signals used in motion-control applications. WG1# is multiplexed with P6.0, WG2# is multiplexed with P6.
SIGNAL DESCRIPTIONS 8XC196MD. Table B-9 lists the same information for the 8XC196MH. Table B-7 defines the symbols used to represent the pin status. Refer to the DC Characteristics table in the datasheet for actual specifications for VOL, VIL, VOH, and VIH. Table B-7.
8XC196MC, MD, MH USER’S MANUAL Table B-8. 8XC196MC and MD Default Signal Conditions (Continued) Alternate Functions Port Signals During RESET# Active Upon RESET# Inactive (Note 14) Idle Powerdown (Note 13) P6.3 WG2 WK1 WK1 (Note 13) P6.4 WG3# WK1 WK1 (Note 13) (Note 13) P6.5 WG3 WK1 WK1 (Note 13) (Note 13) P6.6 PWM0 WK0 — (Note 13) (Note 13) P6.7 PWM1 WK0 — (Note 13) (Note 13) P7.1:0 (Note 15) EPA5:4 WK1 (Note 1) — (Note 12) (Note 12) P7.
SIGNAL DESCRIPTIONS Table B-9. 8XC196MH Default Signal Conditions Alternate Functions Port Signals During RESET# Active Upon RESET# Inactive (Note 12) Idle Powerdown HiZ P0.5:0 ACH5:0 HiZ — HiZ P0.6 ACH6/T1CLK HiZ — HiZ HiZ P0.7 ACH7/T1DIR HiZ — HiZ HiZ P1.0 TXD0 WK1 WK1 (Note 10) (Note 10) P1.1 RXD0 WK1 WK1 (Note 10) (Note 10) P1.2 TXD1 WK1 WK1 (Note 10) (Note 10) P1.3 RXD1 WK1 WK1 (Note 10) (Note 10) P2.0 EPA0 WK1 (Note 1) WK1 (Note 10) (Note 10) P2.
8XC196MC, MD, MH USER’S MANUAL Table B-9. 8XC196MH Default Signal Conditions (Continued) Port Signals Alternate Functions During RESET# Active Upon RESET# Inactive (Note 12) Idle Powerdown — XTAL1 Osc input, HiZ — Osc input, HiZ Osc input, HiZ — XTAL2 Osc output, LoZ0/1 — Osc output, LoZ0/1 (Note 5) NOTES: 1. These pins also control test mode entry. 2. If Disable Reset Out = 0, pin is LoZ0. Else if Disable Reset Out =1, pin is HiZ. 3. If EA# = 0, Port 3 and Port 4 = HiZ.
C Registers
APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-1 lists the modules and major components of the device with their related configuration and status registers. Table C-2 lists the registers, arranged alphabetically by mnemonic, along with their names, addresses, and reset values. Following the tables, individual descriptions of the registers are arranged alphabetically by mnemonic. Table C-1.
8XC196MC, MD, MH USER’S MANUAL Table C-2.
REGISTERS Table C-2.
8XC196MC, MD, MH USER’S MANUAL Table C-2.
REGISTERS Table C-2.
8XC196MC, MD, MH USER’S MANUAL AD_COMMAND Address: Reset State: AD_COMMAND 1FACH 80H The A/D command (AD_COMMAND) register selects the A/D channel number to be converted, controls whether the A/D converter starts immediately or with an EPA command, and selects the conversion mode. 7 0 — Bit Number M1 M0 GO ACH3 Bit Mnemonic ACH2 ACH1 ACH0 Function 7 — Reserved; for compatibility with future devices, write zeros to these bits. 6:5 M1:0 A/D Mode† These bits determine the A/D mode.
REGISTERS AD_RESULT (Read) Address: Reset State (MC, MD): Reset State (MH): AD_RESULT (Read) 1FAAH FFC0H 7FC0H The A/D result (AD_RESULT) register consists of two bytes. The high byte contains the eight mostsignificant bits from the A/D converter. The low byte contains the two least-significant bits from a tenbit A/D conversion, indicates the A/D channel number that was used for the conversion, and indicates whether a conversion is currently in progress.
8XC196MC, MD, MH USER’S MANUAL AD_RESULT (Write) Address: Reset State (MC, MD): Reset State (MH): AD_RESULT (Write) 1FAAH FFC0H 7FC0H The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes. 15 8 REFV7 REFV6 REFV5 REFV4 REFV3 REFV2 REFV1 REFV0 7 0 — Bit Number 15:8 — — — Bit Mnemonic REFV7:0 — — — — Function Reference Voltage These bits specify the threshold value.
REGISTERS AD_TEST Address: Reset State (MC, MD): Reset State (MH): AD_TEST 1FAEH C0H 88H The A/D test (AD_TEST) register specifies adjustments for DC offset errors. 7 0 — Bit Number — — OFF1 Bit Mnemonic 7:5 — 4 OFF1 — OFF0 — — Function Reserved; for compatibility with future devices, write zeros to these bits. Offset This bit , along with OFF0 (bit 2) allows you to set the zero offset point. OFF1 OFF0 0 0 1 1 0 1 0 1 no adjustment add 2.5 mV subtract 2.5 mV subtract 5.
8XC196MC, MD, MH USER’S MANUAL AD_TIME Address: Reset State: AD_TIME 1FAFH FFH The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit. This register programs the speed at which the A/D can run — not the speed at which it can convert correctly. Consult the data sheet for recommended values. Initialize the AD_TIME register before initializing the AD_COMMAND register.
REGISTERS CCR0 no direct access† CCR0 The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width. 7 0 LOC1 Bit Number 7:6 LOC0 IRC1 IRC0 ALE Bit Mnemonic LOC1:0 WR BW0 PD Function Lock Bits These two bits control read and write access to the OTPROM during normal operation.
8XC196MC, MD, MH USER’S MANUAL CCR0 no direct access† CCR0 (Continued) The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
REGISTERS CCR1 no direct access† CCR1 The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. 7 0 1 1 Bit Number Bit Mnemonic 0 1 WDE BW1 IRC2 0 Function 7:6 1 To guarantee proper operation, write ones to these bits. 5 0 To guarantee proper operation, write zero to this bit. 4 1 To guarantee proper operation, write one to this bit.
8XC196MC, MD, MH USER’S MANUAL CCR1 no direct access† CCR1 (Continued) The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. 7 0 1 1 Bit Number Bit Mnemonic 1 IRC2 0 1 WDE BW1 IRC2 0 Function Ready Control This bit, along with IRC0 (CCR0.4), IRC1 (CCR0.5), and the READY pin determine the number of wait states that can be inserted into the bus cycle.
REGISTERS COMPx_CON Address: Reset State: COMP x_CON x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD) Table C-3 The EPA compare control (COMPx_CON) registers determine the function of the EPA compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT RT 7 x = 1, 3, 5 7 0 TB TB CE M1 M0 RE AD ROT RT Time Base Select Specifies the reference timer.
8XC196MC, MD, MH USER’S MANUAL COMPx_CON Address: Reset State: COMPx_CON (Continued) x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD) Table C-3 The EPA compare control (COMPx_CON) registers determine the function of the EPA compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT RT 7 x = 1, 3, 5 2 0 TB WGR AD CE M1 M0 RE AD ROT RT A/D Conversion, Waveform Generator Reload The function of this bit depends on the EPA channel.
REGISTERS COMPx_TIME Address: Reset State: COMP x_TIME x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD Table C-3 The EPA compare x time (COMPx_TIME) registers are the event-time registers for the EPA compare channels; they are functionally identically to the EPAx_TIME registers. The EPA triggers a compare event when the reference timer matches the value in COMPx_TIME. 15 0 EPA Event Time Value Bit Number 15:0 Function EPA Event Time Value Write the desired compare event time to this register. Table C-3.
8XC196MC, MD, MH USER’S MANUAL EPAx_CON Address: Reset State: EPAx_CON x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) Table C-4 The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT ON/RT 7 x = 1, 3, 5 Bit Number 7 0 TB CE M1 M0 Bit Mnemonic TB RE AD ROT ON/RT Function Time Base Select Specifies the reference timer.
REGISTERS EPAx_CON Address: Reset State: EPAx_CON (Continued) x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) Table C-4 The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. 7 x = 0, 2, 4 0 TB CE M1 M0 RE WGR ROT ON/RT 7 x = 1, 3, 5 Bit Number 3 0 TB CE M1 Bit Mnemonic RE M0 RE AD ROT ON/RT Function Re-enable Re-enable applies to the compare mode only.
8XC196MC, MD, MH USER’S MANUAL EPAx_CON Address: Reset State: EPAx_CON (Continued) x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) Table C-4 The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels.
REGISTERS EPAx_TIME Address: Reset State: EPAx_TIME x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) Table C-5 The EPA time (EPAx_TIME) registers are the event-time registers for the EPA channels. In capture mode, the value of the reference timer is captured in EPAx_TIME when an input transition occurs. Each event-time register is buffered, allowing the storage of two capture events at once.
8XC196MC, MD, MH USER’S MANUAL FREQ_CNT Address: Reset State: FREQ_CNT (8XC196MD) 1FBAH 00H Read the frequency generator count (FREQ_CNT) register to determine the current value of the down-counter. 7 0 8XC196MD Count Bit Number Function 7:0 Count This register contains the current down-counter value.
REGISTERS FREQ_GEN Address: Reset State: FREQ_GEN (8XC196MD) 1FB8H 00H The frequency (FREQ_GEN) register holds a programmed value that specifies the output frequency. This value is reloaded into the down-counter each time the counter reaches 0. 7 0 8XC196MD Output Frequency Bit Number Function 7:0 Output Frequency Use the following formula to calculate the FREQ value for the desired output frequency and write this value to the frequency register.
8XC196MC, MD, MH USER’S MANUAL GEN_CON Address: Reset State: GEN_CON (8XC196MH) 1FA0H 00H The GEN_CON register controls whether an internal reset asserts the external RESET# signal and indicates the source of the most recent reset.
REGISTERS INT_MASK Address: Reset State: INT_MASK 0008H 00H The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register. Interrupt calls cannot occur immediately following this instruction. POPF or POPA restores it.
8XC196MC, MD, MH USER’S MANUAL INT_MASK1 Address: Reset State: INT_MASK1 0013H 00H The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
REGISTERS INT_PEND Address: Reset State: INT_PEND 0009H 00H When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
8XC196MC, MD, MH USER’S MANUAL INT_PEND1 Address: Reset State: INT_PEND1 0012H 00H When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
REGISTERS ONES_REG Address: Reset State: ONES_REG 02H FFFFH The two-byte ones register (ONES_REG) is always equal to FFFFH. It is useful as a fixed source of all ones for comparison operations. 15 0 One Bit Number 15:0 Function One These bits are always equal to FFFFH.
8XC196MC, MD, MH USER’S MANUAL Px_DIR Address: Reset State: Px_DIR x = 2, 5 (8XC196MC) x = 2, 5, 7 (8XC196MD) x = 1, 2, 5 (8XC196MH) Table C-6 Each pin of port x can operate in any of the standard I/O modes of operation: complementary output, open-drain output, or high-impedance input. The port x I/O direction (Px_DIR) register determines the I/O direction for each port x pin. The register settings for an open-drain output or a high-impedance input are identical.
REGISTERS Px_MODE Address: Reset State: Px_MODE x = 2, 5 (8XC196MC) x = 2, 5, 7 (8XC196MD) x = 1, 2, 5 (8XC196MH) Table C-7 Each bit of the port x mode (Px_MODE) register controls whether the corresponding pin functions as a standard I/O port pin or as a special-function signal.
8XC196MC, MD, MH USER’S MANUAL Px_MODE Table C-8. Special-function Signals for Ports 1, 2, 5, 6 Port 1 (8XC196MH) Pin Special-function Signal Port 2 (8XC196MC, MD) Pin Special-function Signal Port 2 (8XC196MH) Pin P1.0 TXD0 P2.0 EPA0/PVER P1.1 RXD0 P2.1 EPA1/PALE# P2.1 SCLK0#/BCLK0/PALE# P1.2 TXD1 P2.2 EPA2/PROG# P2.2 EPA1/PROG# P1.3 RXD1 P2.3 EPA3 P2.3 COMP3 P2.4 COMP0/AINC# P2.4 COMP0/AINC# P2.5 COMP1/PACT# P2.5 COMP1/PACT# P2.6 COMP2/CPVER P2.6 COMP2/CPVER P2.
REGISTERS Px_PIN Address: Reset State: Px_PIN x = 0–5 (8XC196MC, MH) x = 0–5, 7 (8XC196MD) Table C-9 Each bit of the port x pin input (Px_PIN) register reflects the current state of the corresponding pin, regardless of the pin configuration.
8XC196MC, MD, MH USER’S MANUAL Px_REG Address: Reset State: Px_REG x = 2–5 (8XC196MC) x = 2–5, 7 (8XC196MD) x = 1–5 (8XC196MH) Table C-10 For an input, set the corresponding port x data output (Px_REG) register bit. For an output, write the data to be driven out by each pin to the corresponding bit of Px_REG. When a pin is configured as standard I/O (Px_MODE.y = 0), the result of a CPU write to P x_REG is immediately visible on the pin. When a pin is configured as a special-function signal (Px_MODE.
REGISTERS PI_MASK Address: Reset State: PI_MASK 1FBCH AAH The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM).
8XC196MC, MD, MH USER’S MANUAL PI_MASK Address: Reset State: PI_MASK (Continued) 1FBCH AAH The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM).
REGISTERS PI_PEND Address: Reset State: PI_PEND 1FBEH AAH When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by setting a PI_PEND bit.
8XC196MC, MD, MH USER’S MANUAL PI_PEND Address: Reset State: PI_PEND (Continued) 1FBEH AAH When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by setting a PI_PEND bit.
REGISTERS PPW no direct access PPW The programming pulse width (PPW) register is loaded from the external EPROM (locations 14H and 15H for the 8XC196MC and MD; locations 4014H and 4015H for the 8XC196MH) in auto programming mode. The PPW_VALUE determines the programming pulse width.
8XC196MC, MD, MH USER’S MANUAL PSW no direct access PSW The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
REGISTERS PSW no direct access PSW (Continued) The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
8XC196MC, MD, MH USER’S MANUAL PTSSEL Address: Reset State: PTSSEL 0004H 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
REGISTERS PTSSRV Address: Reset State: PTSSRV 0006H 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
8XC196MC, MD, MH USER’S MANUAL PWM_COUNT Address: Reset State: PWM_COUNT (read only) 1FB6H 00H The PWM count (PWM_COUNT) register provides the current value of the decremented period counter. 7 0 PWM Count Value Bit Number 7:0 Function PWM Count Value This register contains the current value of the decremented period counter.
REGISTERS PWM_PERIOD Address: Reset State: PWM_PERIOD 1FB4H 00H The PWM period (PWM_PERIOD) register controls the period of the PWM outputs. It contains a value that determines the number of state counts necessary for incrementing the PWM counter. The value of PWM_PERIOD is loaded into the PWM period count register whenever the count equals zero. 7 0 PWM Period Bit Number 7:0 Function PWM Period This register controls the period of the PWM outputs.
8XC196MC, MD, MH USER’S MANUAL PWMx_CONTROL Address: Reset State: PWMx_CONTROL x = 0–1 1FB0H, 1FB2H 00H The PWM control (PWMx_CONTROL) register determines the duty cycle of the PWM x channel. A zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in this register causes the PWM to have its maximum duty cycle (99.6% duty cycle). 7 0 PWM Duty Cycle Bit Number 7:0 Function PWM Duty Cycle This register controls the PWM duty cycle.
REGISTERS SBUFx_RX Address: Reset State: SBUFx_RX x = 0–1 (8XC196MH) 1F80H, 1F88H 00H The serial port receive buffer x (SBUFx_RX) register contains data received from serial port x. The serial port receiver is buffered and can begin receiving a second data byte before the first byte is read. Data is held in the receive shift register until the last data bit is received, then the data byte is loaded into SBUFx_RX.
8XC196MC, MD, MH USER’S MANUAL SBUFx_TX Address: Reset State: SBUFx_TX x = 0–1 (8XC196MH) 1F82H, 1F8AH 00H The serial port transmit buffer x (SBUFx_TX) register contains data that is ready for transmission. In modes 1, 2, and 3, writing to SBUF x_TX starts a transmission. In mode 0, writing to SBUFx_TX starts a transmission only if the receiver is disabled (SPx_CON.3=0).
REGISTERS SP Address: Reset State: SP 18H XXXXH The system’s stack pointer (SP) can point anywhere in internal or external memory; it must be word aligned and must always be initialized before use. The stack pointer is decremented before a PUSH and incremented after a POP, so the stack pointer should be initialized to two bytes (in 64-Kbyte mode) or four bytes (in 1-Mbyte mode) above the highest stack location.
8XC196MC, MD, MH USER’S MANUAL SPx_BAUD Address: Reset State: SPx_BAUD x = 0–1 (8XC196MH) 1F84H, 1F8CH 0000H The serial port baud rate x (SP x_BAUD) register selects the serial port x baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate. The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum BAUD_VALUE is 0000H when using XTAL1 and 0001H when using BCLKx.
REGISTERS SPx_CON Address: Reset State: SPx_CON x = 0–1 (8XC196MH) 1F83H, 1F8BH 00H The serial port control (SPx_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. 7 Bit Number 0 M2 8XC196MH DIR PAR TB8 Bit Mnemonic REN PEN M1 M0 Function 7 M2 See description for bits 0 and 1. 6 DIR Synchronous Clock Direction This bit determines the direction of the clock during synchronous mode.
8XC196MC, MD, MH USER’S MANUAL SPx_STATUS Address: Reset State: SPx_STATUS x = 0–1 (8XC196MH) 1F81H, 1F89H 00H The serial port status (SPx_STATUS) register contains bits that indicate the status of serial port x. 7 RPE/RB8 8XC196MH Bit Number Bit Mnemonic 7 RPE/RB8 0 RI TI FE TXE OE — — Function Received Parity Error/Received Bit 8 RPE is set if parity is disabled (SPx_CON.2 = 0) and the ninth data bit received is high. RB8 is set if parity is enabled (SP x_CON.
REGISTERS T1CONTROL Address: Reset State: T1CONTROL 1F78H 00H The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
8XC196MC, MD, MH USER’S MANUAL T1RELOAD Address: Reset State: T1RELOAD 1F72H XXXXH The timer 1 reload (T1RELOAD) register contains a reinitialization value for timer 1. The value of T1RELOAD is loaded into TIMER1 when timer 1 overflows or underflows and both quadrature clocking and the reload function are enabled (i.e., T1CONTROL.5:0 = 1). 15 0 Timer 1 Reload Value Bit Number 15:0 Function Timer 1 Reload Value Write the timer 1 reinitialization value to this register.
REGISTERS T2CONTROL Address: Reset State: T2CONTROL 1F7CH 00H The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. 7 0 CE Bit Number 7 UD M2 M1 M0 Bit Mnemonic CE P2 P1 P0 Function Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
8XC196MC, MD, MH USER’S MANUAL TIMERx Address: Reset State: TIMERx x = 1–2 1F7AH, 1F7EH 0000H This register contains the value of timer x. This register can be written, allowing timer x to be initialized to a value other than zero. 15 0 Timer Value Bit Number 15:0 Function Timer Value Read the current timer x value from this register or write a new timer x value to this register.
REGISTERS USFR Address: Reset State (MC, MD): Reset State (MH): USFR 1FF6H 02H XXH The unerasable PROM (USFR) register contains two bits that disable external fetches of data and instructions and another that detects a failed oscillator. These bits can be programmed, but cannot be erased. WARNING: These bits can be programmed, but can never be erased. Programming these bits makes dynamic failure analysis impossible.
8XC196MC, MD, MH USER’S MANUAL WATCHDOG Address: Reset State: WATCHDOG 0AH XXH Unless it is cleared every 64K state times, the watchdog timer resets the device. To clear the watchdog timer, send “1EH” followed immediately by “E1H” to location 0AH. Clearing this register the first time enables the watchdog with an initial value of 0000H, which is incremented once every state time. After it is enabled, the watchdog can be disabled only by a reset.
REGISTERS WG_COMPx Address: Reset State: WG_COMP x x = 1–3 1FC2H,1FC4H,1FC6H 0000H The phase compare (WG_COMPx) register controls the duty cycle of each phase. Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted. Changing the WG_RELOAD value changes both the carrier period and the duty cycle because the outputs remain asserted for a constant length of time, while the counter takes longer to cycle.
8XC196MC, MD, MH USER’S MANUAL WG_CONTROL Address: Reset State (MC, MD): Reset State (MH): WG_CONTROL 1FCCH 00C0H 8000H The waveform generator control (WG_CONTROL) register controls the operating mode, dead time, and count direction, and enables and disables the counter. 15 8 — M2 M1 M0 CS EC DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 7 0 Bit Number Bit Mnemonic 15 — 14:12 M2:0 Function Reserved; for compatibility with future devices, write zero to this bit.
REGISTERS WG_COUNTER Address: Reset State (MC, MD): Reset State (MH): WG_COUNTER 1FCAH XXXXH 0000H You can read the waveform generator counter (WG_COUNTER) register to determine the current counter value. 15 0 Counter Value Bit Number 15:0 Function Counter Value This register reflects the current counter value.
8XC196MC, MD, MH USER’S MANUAL WG_OUTPUT (Port 6) Address: Reset State: WG_OUTPUT (Port 6) 1FC0H 0000H The port 6 output configuration (WG_OUTPUT) register controls port 6 functions. If you are using port 6 for general-purpose outputs, write C0H (for active-high outputs) or 00H (for active-low outputs) to the high byte of WG_OUTPUT and write the desired pin values to the low byte.
REGISTERS WG_OUTPUT (Waveform Generator) Address: Reset State: WG_OUTPUT (Waveform Generator) 1FC0H 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT. 15 8 OP1 OP0 SYNC PE7 PE6 PH3.2 PH2.2 PH1.2 P7 P6 PH3.
8XC196MC, MD, MH USER’S MANUAL WG_OUTPUT (Waveform Generator) Address: Reset State: WG_OUTPUT (Waveform Generator) (Continued) 1FC0H 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT. 15 8 OP1 OP0 SYNC PE7 PE6 PH3.
REGISTERS WG_OUTPUT (Waveform Generator) , Table C-11. Output Configuration Output Values PHx.2 PHx.1 Output Polarities PHx.0 WGx WGx# WGx WGx# Always Low 1 0 0 Low Low Always Low 1 0 1 Low WG_EVEN# Always Low 1 1 0 WG_ODD Low 1 1 1 WG_ODD WG_EVEN NOTE: Always Low This table assumes active-high outputs (OP1=OP0=1).
8XC196MC, MD, MH USER’S MANUAL WG_PROTECT Address: Reset State (MC, MD) Reset State (MH): WG_PROTECT 1FCEH F0H E0H The waveform protection (WG_PROTECT) register enables and disables the outputs and the protection circuitry. It also selects either level-sensitive or edge-triggered EXTINT interrupts, and selects which level or edge will generate an EXTINT interrupt request.
REGISTERS WG_RELOAD Address: Reset State: WG_RELOAD 1FC8H 0000H The waveform generator reload (WG_RELOAD) register and the phase compare registers (WG_COMPx) control the carrier period and duty cycle. Write a value to the reload register to establish the carrier period. Changing the WG_RELOAD value changes both the carrier period and the duty cycle because the outputs remain asserted for a constant length of time, while the counter takes longer to cycle.
8XC196MC, MD, MH USER’S MANUAL WSR Address: Reset State: WSR 0014H 00H The window selection register (WSR) maps sections of RAM into the top of the lower register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA restores it. 7 0 — W6 Bit Number Bit Mnemonic W5 W4 W3 W2 W1 W0 Function 7 — Reserved; for compatibility with future devices, write zero to this bit. 6:0 W6:0 Window Selection These bits specify the window size and number.
REGISTERS WSR Table C-12.
8XC196MC, MD, MH USER’S MANUAL WSR Table C-12.
REGISTERS ZERO_REG Address: Reset State: ZERO_REG 00H 0000H The two-byte zero register (ZERO_REG) is always equal to zero. It is useful as a fixed source of the constant zero for comparisons and calculations. 15 0 Zero Bit Number 15:0 Function Zero This register is always equal to zero.
Glossary
GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this manual. (Chapter 1 discusses notational conventions and general terminology.) absolute error The maximum difference between corresponding actual and ideal code transitions. Absolute error accounts for all deviations of an actual A/D converter from an ideal converter. accumulator A register or storage location that forms the result of an arithmetic or logical operation.
8XC196MC, MD, MH USER’S MANUAL CCBs Chip configuration bytes. The chip configuration registers (CCRs) are loaded with the contents of the CCBs after a device reset, unless the device is entering programming modes, in which case the PCCBs are used. CCRs Chip configuration registers. Registers that specify the environment in which the device will be operating.
GLOSSARY deassert The act of making a signal inactive (disabled). The polarity (high or low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To deassert RD# is to drive it high; to deassert ALE is to drive it low. differential nonlinearity The difference between the actual code width and the ideal one-LSB code width of the terminal-based characteristic of an A/D converter.
8XC196MC, MD, MH USER’S MANUAL full-scale error The difference between the ideal and actual input voltage corresponding to the final (full-scale) code transition of an A/D converter. hold latency The time it takes the microcontroller to assert HLDA# after an external device asserts HOLD#. ideal characteristic The characteristic of an ideal A/D converter. An ideal characteristic is unique: its first code transition occurs when the input voltage is 0.
GLOSSARY LSB 1) Least-significant bit of a byte or least-significant byte of a word. 2) In an A/D converter, the reference voltage divided by 2n, where n is the number of bits to be converted. For a 10-bit converter with a reference voltage of 5.12 volts, one LSB is equal to 5.0 millivolts (5.12 ÷ 210). maskable interrupts All interrupts except unimplemented opcode, software trap, and NMI.
8XC196MC, MD, MH USER’S MANUAL nonmaskable interrupts Interrupts that cannot be masked (disabled) and cannot be assigned to the PTS for processing. The nonmaskable interrupts are unimplemented opcode, software trap, and NMI. nonvolatile memory Read-only memory that retains its contents when power is removed. Many MCS® 96 microcontrollers are available with either masked ROM, EPROM, or OTPROM.
GLOSSARY program memory A partition of memory where instructions can be stored for fetching and execution. protected instruction An instruction that prevents an interrupt from being acknowledged until after the next instruction executes. The protected instructions are DI, EI, DPTS, EPTS, POPA, POPF, PUSHA, and PUSHF. PSW Processor status word.
8XC196MC, MD, MH USER’S MANUAL PWM Pulse-width modulated (outputs). The 8XC196Mx devices have several options for producing PWM outputs: the generic pulse-width modulator modules, the waveform generator, and the EPA with or without the PTS. The 8XC196MD also has a frequency generator that produces PWM outputs. quantizing error An unavoidable A/D conversion error that results simply from the conversion of a continuous voltage to its integer digital representation. Quantizing error is always ± 0.
GLOSSARY sample time The period of time that the sample window is open. (That is, the length of time that the input channel is actually connected to the sample capacitor.) sample time uncertainty The variation in the sample time. sample window The period of time that begins when the sample capacitor is attached to a selected channel of an A/D converter and ends when the sample capacitor is disconnected from the selected channel.
8XC196MC, MD, MH USER’S MANUAL special interrupt Any of the three nonmaskable interrupts (unimplemented opcode, software trap, or NMI). special-purpose memory A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and several reserved locations. standard interrupt Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine.
GLOSSARY transfer function errors Errors inherent in an analog-to-digital conversion process: quantizing error, zero-offset error, full-scale error, differential nonlinearity, and nonlinearity. Errors that are hardware-dependent, rather than being inherent in the process itself, include feedthrough, repeatability, channel-to-channel matching, offisolation, and VCC rejection errors. UART Universal asynchronous receiver and transmitter. A part of the serial I/O port.
Index
INDEX #, defined, 1-3, A-1 16-bit data bus read cycles, 15-14 timing diagram, 15-15 write cycles, 15-14 8-bit data bus read cycles, 15-16 timing diagram, 15-17 write cycles, 15-16 A A/D command register, 12-8, C-6 A/D converter, 2-11, 12-1–12-18 actual characteristic, 12-16 and port 0 reads, 12-13 and PTS, 5-32–5-37 block diagram, 12-1 calculating result, 12-9, 12-13 calculating series resistance, 12-10 characteristics, 12-15–12-18 conversion time, 12-6 determining status, 12-9 errors, 12-13–12-18 hardware
8XC196MC, MD, MH USER’S MANUAL AND instruction, A-2, A-8, A-41, A-42, A-48, A-53 ANDB instruction, A-2, A-8, A-9, A-42, A-43, A-48, A-53 ANGND, 12-5, 13-1, B-14 ApBUILDER software, downloading, 1-10 Application notes, ordering, 1-6 Arithmetic instructions, A-47, A-48, A-52, A-53 Assert, defined, 1-3 Auto programming mode, 16-25–16-28 algorithm, 16-28 circuit, 16-25–16-26 memory map, 16-27 PCCB, 16-27 security key programming, 16-29 standard, 15-22–15-24 write strobe, 15-25–15-26 Bus-control signals, 15-21
INDEX Clock external, 13-7 generator, 2-7, 13-7, 13-8 internal, and idle mode, 14-4, 14-5 phases, internal, 2-8 CLR instruction, A-2, A-10, A-41, A-47, A-52 CLRB instruction, A-2, A-11, A-41, A-47, A-52 CLRC instruction, A-3, A-11, A-46, A-51, A-57 CLRVT instruction, A-3, A-11, A-46, A-51, A-57 CMP instruction, A-3, A-11, A-43, A-47, A-52 CMPB instruction, A-3, A-11, A-44, A-47, A-52 CMPL instruction, A-2, A-12, A-45, A-47, A-52 Code execution, 2-5, 2-6 COMP0_TIME, C-68 COMP1_CON, C-68 COMP1_TIME, C-68 COM
8XC196MC, MD, MH USER’S MANUAL re-enabling the compare event, 11-20, 11-22 reloading the waveform generator, 11-20, 11-23, C-16 resetting the timer in compare mode, 11-21 resetting the timers, 11-21, 11-23 selecting the capture/compare event, 11-19 selecting the compare event, 11-22 selecting the time base, 11-19, 11-22 selecting up or down counting, 11-16, 11-17 signals, 11-2 starting an A/D conversion, 11-20, 11-23, C-16 See also port 1, port 6, PWM, timer/counters EPA compare control x register, 11-22,
INDEX Hypertext manuals and datasheets, downloading, 1-10 I Idle mode, 2-11, 13-13, 14-4–14-5 entering, 14-5 pin status, B-23, B-25 timeout control, 11-7 IDLPD instruction, A-2, A-16, A-46, A-51, A-57 IDLPD #1, 14-5 IDLPD #2, 14-6 illegal operand, 13-9, 13-12 Immediate addressing, 3-6 INC instruction, A-2, A-16, A-41, A-47, A-52 INCB instruction, A-2, A-17, A-41, A-47, A-52 Indexed addressing, 3-9 and register RAM, 4-10 and windows, 4-19 Indirect addressing, 3-6 and register RAM, 4-10 with autoincrement,
8XC196MC, MD, MH USER’S MANUAL JVT instruction, A-3, A-5, A-23, A-45, A-50, A-56 L Latency‚ See bus-hold protocol‚ interrupts LCALL instruction, A-3, A-23, A-45, A-50, A-56 LD instruction, A-2, A-23, A-44, A-49, A-55 LDB instruction, A-2, A-23, A-44, A-49, A-55 LDBSE instruction, A-3, A-24, A-44, A-49, A-55 LDBZE instruction, A-3, A-24, A-44, A-49, A-55 Level-sensitive input, B-13 Literature, 1-11 LJMP instruction, A-2, A-24, A-49, A-55 Logical instructions, A-48, A-53 LONG-INTEGER, defined, 3-4 Lookup ta
INDEX ORB instruction, A-2, A-28, A-43, A-48, A-53 Oscillator and powerdown mode, 14-5 external crystal, 13-6 on-chip, 13-5 OTPROM controlling access to internal memory, 16-3–16-6 controlling fetches from external memory, 16-6–16-7 memory map, 16-2 programming, 16-1–16-33 See also programming modes ROM-dump mode, 16-30 verifying, 16-30 Overflow (V) flag, A-4, A-5, A-21, A-22 Overflow-trap (VT) flag, A-4, A-5, A-11, A-22, A-23 P P0.7:0, B-17 P0.7:4 and programming modes, 16-14 P0_PIN, C-69 P1.3:0, B-17 P1.
8XC196MC, MD, MH USER’S MANUAL SFRs, 6-6, 14-3 Port 3, B-18 addressing, 6-14 idle, powerdown, reset status, B-23, B-25 operation, 6-15–6-16 overview, 6-1 pin configuration, 6-14 structure, 6-15 Port 4, B-18 addressing, 6-14 idle, powerdown, reset status, B-23, B-25 operation, 6-15–6-16 overview, 6-1 pin configuration, 6-14 structure, 6-15 Port 5, B-18 considerations, 6-12 idle, powerdown, reset status, B-23, B-25 operation, 6-4, 6-12 overview, 6-1 pin configuration, 6-12 SFRs, 6-6, 14-3 Port 6, B-18 config
INDEX instructions, A-51, A-57 interrupt latency, 5-11 interrupt processing flow, 5-2 routine, defined, 5-1 serial I/O modes, 5-37–5-58 single transfer mode, 5-27 synchronous serial I/O receive mode, 5-47–5-50 synchronous serial I/O transmit mode, 5-43–5-46 vectors, memory locations, 4-3 See also PWM PTS select register, 5-14, C-42 PTS service register, 5-26, C-43 PTSCB, 5-4, 5-9 A/D scan mode, 5-33 block transfer mode, 5-31 memory locations, 4-3 PTSCON register, 5-27 PTSCOUNT register, 5-25 single transfe
8XC196MC, MD, MH USER’S MANUAL FREQ_CNT, 8-4, C-22 FREQ_GEN, 8-3, C-23 GEN_CON, 13-9, C-24 grouped by modules, C-1 INT_MASK, 5-15, C-25 INT_MASK1, 5-16, 7-2, C-26 INT_PEND, 5-21, 7-3, C-27 INT_PEND1, 5-22, 7-3, C-28 naming conventions, 1-4 ONES_REG, C-29 P0_PIN, 6-3, 6-4 P1_MODE considerations, 6-12 P1_PIN, 6-3, 6-4, 7-3 P2_MODE considerations, 6-12 P2_REG considerations, 6-12 P5_MODE considerations, 6-12, 6-13 PI_MASK, 5-17, 7-4, C-35 PI_PEND, 5-23, 7-4, C-37 PPW, 16-8, C-39 PSW, C-40 PTSSEL, 5-14, C-42 P
INDEX RST instruction, 3-11, 13-9, 13-12, A-3, A-31, A-46, A-51, A-57 Run-time programming, 16-32–16-33 code example, 16-33 RXD, B-20 and SIO port mode 0, 7-5, 7-7 and SIO port modes 1, 2, and 3, 7-7 S Sampled input, B-13 SBUFx_RX, C-70 SBUFx_TX, C-70 SCALL instruction, A-3, A-31, A-41, A-47, A-50, A-55, A-56 SCLKx#, 7-2 Security key verification, 16-30 Serial I/O modes, See PTS Serial I/O port‚ See SIO port Serial port control x register, 7-10, C-51 Serial port receive buffer x register, C-47 Serial port
8XC196MC, MD, MH USER’S MANUAL SJMP instruction, A-2, A-36, A-41, A-47, A-49, A-55 SKIP instruction, A-2, A-36, A-41, A-51, A-57 Slave programming mode, 16-15–16-24 address/command decoder routine, 16-19, 16-20 algorithm, 16-19–16-24 circuit, 16-16 dump-word routine, 16-19, 16-23 entering, 16-19 program-word routine, 16-19, 16-21 security key programming, 16-15 timings, 16-22, 16-24 Software addressing modes, 3-9 conventions, 3-9–3-11 device reset, 13-12 interrupt service routines, 5-19 linking subroutines
INDEX Timing diagrams 16-bit data bus, 15-15 8-bit data bus, 15-17 BUSWIDTH, 15-12 READY, 15-19 system bus timing, 15-32 Timing requirements BUSWIDTH, 15-13 READY, 15-18 TRAP instruction, 5-6, A-2, A-39, A-46, A-50, A-55, A-56 TRAP interrupt, 5-4 TXD, B-21 and SIO port mode 0, 7-5 U UART, 2-9, 7-1 Unerasable PROM register, 16-7, C-57 Unimplemented opcode interrupt, 3-11, 5-4, 5-6, 5-9 Units of measure, defined, 1-5 Universal asynchronous receiver and transmitter‚ See UART UPROM, 16-6 programming, 16-6–16-
8XC196MC, MD, MH USER’S MANUAL WSR values and direct addresses, 4-15 WORD, defined, 3-2 World Wide Web, 1-11 WR#, B-22 idle, powerdown, reset status, B-23, B-25 WRH#, B-22 Write cycles 16-bit data bus, 15-14 8-bit data bus, 15-16 Write strobe mode example system, 15-26 signals, 15-25 WRL#, B-22 WSR, 4-13, C-68 X X, defined, 1-5 x, defined, 1-3 XCH instruction, A-2, A-3, A-40, A-41, A-49, A-55 XCHB instruction, A-2, A-3, A-40, A-41, A-49, A-55 XOR instruction, A-2, A-40, A-43, A-48, A-53 XORB instruction,
