27279502.
8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ Embedded Microcontroller User’s Manual May 1996 Order Number 272795-002
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor variations to this specification known as errata.
CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3 1.3 RELATED DOCUMENTS .............................................................................................. 1-5 1.3.1 Data Sheet ................................................................................................................
8XC251SA, SB, SP, SQ USER’S MANUAL 3.3.2.3 Extended Stack Pointer, SPX ............................................................................3-15 3.4 SPECIAL FUNCTION REGISTERS (SFRS) ............................................................... 3-16 CHAPTER 4 DEVICE CONFIGURATION 4.1 CONFIGURATION OVERVIEW .................................................................................... 4-1 4.2 DEVICE CONFIGURATION ................................................................................
CONTENTS 5.4 BIT INSTRUCTIONS ................................................................................................... 5-11 5.4.1 Bit Addressing .........................................................................................................5-11 5.5 CONTROL INSTRUCTIONS ....................................................................................... 5-12 5.5.1 Addressing Modes for Control Instructions .............................................................5-13 5.5.
XC251SA, SB, SP, SQ USER’S MANUAL 8.2 TIMER/COUNTER OPERATION................................................................................... 8-1 8.3 TIMER 0......................................................................................................................... 8-3 8.3.1 Mode 0 (13-bit Timer) ...............................................................................................8-4 8.3.2 Mode 1 (16-bit Timer) .....................................................................
CONTENTS 10.2 MODES OF OPERATION............................................................................................ 10-4 10.2.1 Synchronous Mode (Mode 0) ..................................................................................10-4 10.2.1.1 Transmission (Mode 0) ......................................................................................10-4 10.2.1.2 Reception (Mode 0) ............................................................................................10-5 10.2.
8XC251SA, SB, SP, SQ USER’S MANUAL 12.2.2 Power Off Flag ........................................................................................................12-1 12.3 IDLE MODE ................................................................................................................. 12-4 12.3.1 Entering Idle Mode ..................................................................................................12-4 12.3.2 Exiting Idle Mode .........................................................
CONTENTS CHAPTER 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14.1 GENERAL.................................................................................................................... 14-1 14.1.1 Programming Considerations for On-chip Code Memory .......................................14-2 14.1.2 EPROM Devices .....................................................................................................14-3 14.2 PROGRAMMING AND VERIFYING MODES...............................................
8XC251SA, SB, SP, SQ USER’S MANUAL FIGURES Figure 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 x Page Functional Block Diagram of the 8XC251SA, SB, SP, SQ ...........................................2-2 The CPU.......................................................................................................................2-5 Clocking Definitions .......................
CONTENTS FIGURES Figure 8-12 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 10-1 10-2 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 Page T2CON: Timer 2 Control Register ..............................................................................8-17 Programmable Counter Array.......................................................................................9-3 PCA 16-bit Capture Mode .
8XC251SA, SB, SP, SQ USER’S MANUAL FIGURES Figure 13-23 13-24 13-25 13-26 13-27 13-28 14-1 14-2 B-1 B-2 xii Page Bus Diagram for Example 4: 87C251SB/83C251SB in Nonpage Mode ..................13-24 Address Space for Example 4 ..................................................................................13-25 Bus Diagram for Example 5: 80C251SB in Nonpage Mode.....................................13-27 Address Space for Examples 5 and 6 ..................................................................
CONTENTS TABLES Table 1-1 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 8-1 8-2 8-3 9-1 9-2 9-3 10-1 10-2 10-3 Page Intel Application Support Services................................................................................1-7 8XC251SA, SB, SP, SQ Features................................................................................2-3 Address Mappings.......................................................
8XC251SA, SB, SP, SQ USER’S MANUAL TABLES Table 10-4 10-5 10-6 12-1 13-1 13-2 13-3 14-1 14-2 14-3 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 A-21 A-22 A-23 A-24 A-25 A-26 A-27 A-28 B-1 B-2 B-3 C-1 C-2 C-3 xiv Page Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3..................................10-12 Selecting the Baud Rate Generator(s) .....................................................................10-13 Timer 2 Generated Baud Rates .........
CONTENTS TABLES Table C-4 C-5 C-6 C-7 Page Serial I/O SFRs ........................................................................................................... C-4 Timer/Counter and Watchdog Timer SFRs ................................................................. C-4 Programmable Counter Array (PCA) SFRs................................................................. C-5 Register File ..............................................................................................................
1 Guide to This Manual
CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC251SA, SB, SP, SQ† embedded microcontroller, which is the first member of the Intel MCS® 251 microcontroller family. This manual is intended for use by both software and hardware designers familiar with the principles of microcontrollers. 1.1 MANUAL CONTENTS This manual contains 14 chapters and 3 appendices. This chapter, Chapter 1, provides an overview of the manual. This section summarizes the contents of the remaining chapters and appendices.
8XC251SA, SB, SP, SQ USER’S MANUAL Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discusses their configuration for general-purpose I/O, external memory accesses (ports 0, 2), and alternative special functions. Chapter 8, “Timer/Counters and WatchDog Timer” — describes the three on-chip timer/counters and discusses their application.
GUIDE TO THIS MANUAL Appendix B, “Signal Descriptions” — describes the function(s) of each device pin. Descriptions are listed alphabetically by signal name. This appendix also provides a list of the signals grouped by functional category. Appendix C, “Registers” — accumulates, for convenient reference, copies of the register definition figures that appear throughout the manual. A glossary has been included for your convenience. 1.
8XC251SA, SB, SP, SQ USER’S MANUAL Instructions Instruction mnemonics are shown in upper case to avoid confusion. When writing code, either upper case or lower case may be used. Logic 0 (Low) An input voltage level equal to or less than the maximum value of VIL or an output voltage level equal to or less than the maximum value of VOL. See data sheet for values.
GUIDE TO THIS MANUAL Units of Measure 1.
8XC251SA, SB, SP, SQ USER’S MANUAL 1.3.1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually. 8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller (Commercial/Express) 1.3.2 Order Number 272783 Application Notes The following application notes apply to the MCS 251 microcontroller.
GUIDE TO THIS MANUAL 1.4 APPLICATION SUPPORT SERVICES You can get up-to-date technical information from a variety of electronic support systems: the World Wide Web, CompuServe, the FaxBack* service, and Intel’s Brand Products and Applications Support bulletin board service (BBS). These systems are available 24 hours a day, 7 days a week, providing technical information whenever you need it. In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m.
8XC251SA, SB, SP, SQ USER’S MANUAL 1.4.3 FaxBack Service The FaxBack service is an on-demand publishing system that sends documents to your fax machine. You can get product announcements, change notifications, product literature, device characteristics, design recommendations, and quality and reliability information from FaxBack 24 hours a day, 7 days a week. Think of the FaxBack service as a library of technical documents that you can access with your phone.
GUIDE TO THIS MANUAL Any customer with a PC and modem can access the BBS. The system provides automatic configuration support for 1200- through 19200-baud modems. Use these modem settings: no parity, 8 data bits, and 1 stop bit (N, 8, 1). To access the BBS, just dial the telephone number (see Table 1-1 on page 1-7) and respond to the system prompts. During your first session, the system asks you to register with the system operator by entering your name and location.
2 Architectural Overview
CHAPTER 2 ARCHITECTURAL OVERVIEW The 8XC251Sx is the first member of the MCS® 251 microcontroller family. This family of 8-bit microcontrollers is a high-performance upgrade of the widely-used MCS 51® microcontrollers. It extends features and performance while maintaining binary-code compatibility and pin compatibility with the 8XC51FX, so the impact on existing hardware and software is minimal. Typical control applications for the 8XC251Sx include copiers, scanners, CD ROMs, and tape drives.
8XC251SA, SB, SP, SQ USER’S MANUAL I/O Ports and Peripheral Signals System Bus and I/O Ports P0.7:0 P2.7:0 Port 0 Drivers Port 2 Drivers Code OTPROM/ROM 8 Kbytes or 16 Kbytes Data RAM 512 Bytes or 1024 Bytes P1.7:0 P3.
ARCHITECTURAL OVERVIEW 2.1 8XC251SA, SB, SP, SQ ARCHITECTURE Figure 2-1 is a functional block diagram of the 8XC251SA, SB, SP, SQ. The core, which is common to all MCS 251 microcontrollers, is described in section 2.2, “MCS 251 Microcontroller Core.” Each microcontroller type in the family has its own on-chip peripherals, I/O ports, external system bus, size of on-chip RAM, and type and size of on-chip program memory. Table 2-1 lists the distinguishing features of the product.
8XC251SA, SB, SP, SQ USER’S MANUAL The 8XC251Sx has two power-saving modes. In idle mode, the CPU clock is stopped, while clocks to the peripherals continue to run. In powerdown mode, the on-chip oscillator is stopped, and the chip enters a static state. An enabled interrupt or a hardware reset can bring the chip back to its normal operating mode from idle or powerdown. See Chapter 12, “Special Operating Modes,” for details on the power-saving modes.
ARCHITECTURAL OVERVIEW 2.2.1 CPU Figure 2-2 is a functional block diagram of the CPU (central processor unit). The 8XC251Sx fetches instructions from on-chip code memory two bytes at a time, or from external memory in single bytes. The instructions are sent over the 16-bit code bus to the execution unit. You can configure the 8XC251Sx to operate in page mode for accelerated instruction fetches from external memory.
8XC251SA, SB, SP, SQ USER’S MANUAL 2.2.2 Clock and Reset Unit The timing source for the 8XC251Sx can be an external oscillator or an internal oscillator with an external crystal/resonator (see Chapter 11, “Minimum Hardware Setup”). The basic unit of time in MCS 251 microcontrollers is the state time (or state), which is two oscillator periods (see Figure 2-3). The state time is divided into phase 1 and phase 2. The 8XC251Sx peripherals operate on a peripheral cycle, which is six state times.
ARCHITECTURAL OVERVIEW 2.2.3 Interrupt Handler The interrupt handler can receive interrupt requests from eleven sources: seven maskable sources and the TRAP instruction. When the interrupt handler grants an interrupt request, the CPU discontinues the normal flow of instructions and branches to a routine that services the source that requested the interrupt. You can enable or disable the interrupts individually (except for TRAP) and you can assign one of four priority levels to each interrupt.
8XC251SA, SB, SP, SQ USER’S MANUAL The watchdog timer is a circuit that automatically resets the 8XC251Sx in the event of a hardware or software upset. When enabled by software, the watchdog timer begins running, and unless software intervenes, the timer reaches a maximum count and initiates a chip reset. In normal operation, software periodically clears the timer register to prevent the reset.
3 Address Spaces
CHAPTER 3 ADDRESS SPACES MCS® 251 microcontrollers have three address spaces: a memory space, a special function register (SFR) space, and a register file. This chapter describes these address spaces as they apply to all MCS 251 microcontrollers and to the 8XC251Sx in particular. It also discusses the compatibility of the MCS 251 architecture and the MCS® 51 architecture in terms of their address spaces. 3.
8XC251SA, SB, SP, SQ USER’S MANUAL It is convenient to view the unsegmented, 16-Mbyte memory space as consisting of 256 64-Kbyte regions, numbered 00: to FF:. NOTE The memory space in the MCS 251 architecture is unsegmented. The 64Kbyte “regions” 00:, 01:, ..., FF: are introduced only as a convenience for discussions. Addressing in the MCS 251 architecture is linear; there are no segment registers. MCS 251 microcontrollers can have up to 64 Kbytes of on-chip code memory in region FF:.
ADDRESS SPACES The register file (registers R0–R7) comprises four switchable register banks, each having eight registers. The 32 bytes required for the four banks occupy locations 00H–1FH in the on-chip data memory. Figure 3-3 shows how the address spaces in the MCS 51 architecture map into the address spaces in the MCS 251 architecture; details are listed in Table 3-1. The 64-Kbyte code memory for MCS 51 microcontrollers maps into region FF: of the memory space for MCS 251 microcontrollers.
8XC251SA, SB, SP, SQ USER’S MANUAL Memory Address Space 16 Mbytes FFFFH SFR Space 512 Bytes MCS 51 Architecture Code Memory S:1FFH FF:0000H 0000H S:100H FFH 80H MCS 51 Architecture SFRs S:07FH 02:0000H S:000H FFFFH MCS 51 Architecture External Data Memory 01:0000H 0000H Register File 64 Bytes 63 00:0000H 00H MCS 51 Architecture Internal Data Memory FFH 8 0 0 MCS 51 Architecture R. F. 7 A4133-01 Figure 3-3. Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture Table 3-1.
ADDRESS SPACES The 64-Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory region specified by bits 16–23 of the data pointer DPX, i.e., DPXL. DPXL is accessible as register file location 57 and also as the SFR at S:084H (see “Dedicated Registers” on page 3-13). The reset value of DPXL is 01H, which maps the external memory to region 01: as shown in Figure 3-3. You can change this mapping by writing a different value to DPXL.
8XC251SA, SB, SP, SQ USER’S MANUAL Memory Address Space 16 Mbytes FF:FFFFH FF:0000H FE:FFFFH FE:0000H Indirect and Displacement Addressing (16 Mbytes) Regions 02–FD are Reserved 01:FFFFH 01:0000H 00:FFFFH Direct Addressing (64 Kbytes) 00:007FH Bit Addressing (96 Bytes) 00:0080H Register Addressing (32 Bytes) 00:0020H 00:0000H 00:001FH A4385-01 Figure 3-4.
i_mempar.fm5 Page 7 Thursday, June 27, 1996 1:38 PM ADDRESS SPACES † FF:FFF7H External Memory FF:0000H On-chip ROM 8 or 16 Kbytes FE:FFFFH External Memory FE:0000H Regions 02–FD are Reserved 01:FFFFH External Memory 01:0000H 00:FFFFH External Memory On-chip RAM 512 or 1024 Bytes †† 00:0000H Registers R0-R7 † Eight-byte configuration array (FF:FFF8H - FF:FFFFH) †† Four banks of registers R0-R7 (32 bytes, 00:0000H - 00:001FH) A4382-02 Figure 3-5.
8XC251SA, SB, SP, SQ USER’S MANUAL Locations FF:FFF8H–FF:FFFFH are reserved for the configuration array (see Chapter 4, “Device Configuration”). The two configuration bytes for the 8XC251Sx are accessed at locations FF:FFF8H and FF:FFF9H; locations FF:FFFAH–FF:FFFFH are reserved for configuration bytes in future products. Do not attempt to execute code from locations FF:FFF8H–FF:FFFFH. Also, see the caution on page 4-2 regarding execution of code from locations immediately below the configuration array.
ADDRESS SPACES Table 3-2. Minimum Times to Fetch Two Bytes of Code Type of Code Memory State Times On-chip Code Memory 1 External Memory (page mode) 2 External Memory (nonpage mode) 4 NOTE If your program executes exclusively from on-chip ROM/OTPROM/EPROM (not from external memory), beware of executing code from the upper eight bytes of the on-chip ROM/OTPROM/EPROM (FF:1FF8H–FF:1FFFH for 8 Kbytes, FF:3FF8H–FF:3FFFH for 16 Kbytes).
8XC251SA, SB, SP, SQ USER’S MANUAL 3.2.3 External Memory Regions 01:, FE:, and portions of regions 00: and FF: of the memory space are implemented as external memory (Figure 3-5 on page 3-7). For discussions of external memory see “Configuring the External Memory Interface” on page 4-8 and Chapter 13, “External Memory Interface.” 3.3 8XC251SA, SB, SP, SQ REGISTER FILE The 8XC251Sx register file consists of 40 locations: 0–31 and 56–63, as shown in Figure 3-6.
ADDRESS SPACES Byte Registers Note: R10 = B R11 = ACC R8 R9 R10 R11 R12 R13 R14 R15 R0 R1 R2 R3 R4 R5 R6 R7 Register File 56 57 58 59 60 Word Registers 61 62 63 Locations 32-55 are Reserved 24 16 8 25 17 9 26 18 10 27 19 11 28 20 12 29 21 13 30 22 14 31 23 15 0 1 2 3 4 5 6 7 WR24 WR16 WR26 WR18 WR28 WR20 WR30 WR22 WR8 WR0 WR10 WR2 WR12 WR4 WR14 WR6 Dword Registers 0 1 2 3 4 5 6 DR56 = DPX DR60 = SPX DR24 DR28 DR16 DR8 DR0 DR20 DR12 DR4 7 Banks 0-3 A4099-01
8XC251SA, SB, SP, SQ USER’S MANUAL Register file locations 0–7 actually consist of four switchable banks of eight registers each, as illustrated in Figure 3-7. The four banks are implemented as the first 32 bytes of on-chip RAM and are always accessible as locations 00:0000H–00:001FH in the memory address space.† Only one of the four banks is accessible via the register file at a given time. The accessible, or “active,” bank is selected by bits RS1 and RS0 in the PSW register, as shown in Table 3-3.
i_mempar.fm5 Page 13 Thursday, June 27, 1996 2:06 PM ADDRESS SPACES 3.3.1 Byte, Word, and Dword Registers Depending on its location in the register file, a register is addressable as a byte, a word, and/or a dword, as shown on the right side of Figure 3-6. A register is named for its lowest numbered byte location. For example: R4 is the byte register consisting of location 4. WR4 is the word register consisting of registers 4 and 5. DR4 is the dword register consisting of registers 4–7.
i_mempar.fm5 Page 14 Thursday, June 27, 1996 2:06 PM 8XC251SA, SB, SP, SQ USER’S MANUAL Instructions in the MCS 51 architecture use the accumulator as the primary register for data moves and calculations. However, in the MCS 251 architecture, any of registers R1–R15 can serve for these tasks†. As a result, the accumulator does not play the central role that it has in MCS 51 microcontrollers.
i_mempar.fm5 Page 15 Thursday, June 27, 1996 2:06 PM ADDRESS SPACES 3.3.2.2 Extended Data Pointer, DPX Dword register DR56 is the extended data pointer, DPX (Figure 3-8). The lower three bytes of DPX (DPL, DPH, and DPXL) are accessible as SFRs. DPL and DPH comprise the 16-bit data pointer DPTR. While instructions in the MCS 51 architecture always use DPTR as the data pointer, instructions in the MCS 251 architecture can use any word or dword register as a data pointer.
8XC251SA, SB, SP, SQ USER’S MANUAL 3.4 SPECIAL FUNCTION REGISTERS (SFRS) The special function registers (SFRs) reside in their associated on-chip peripherals or in the core. Table 3-5 shows the SFR address space with the SFR mnemonics and reset values. SFR addresses are preceded by “S:” to differentiate them from addresses in the memory space. Unoccupied locations in the SFR space (the shaded locations in Table 3-5) are unimplemented, i.e., no register exists.
ADDRESS SPACES Table 3-5.
8XC251SA, SB, SP, SQ USER’S MANUAL The following tables list the mnemonics, names, and addresses of the SFRs: Table 3-6 — Core SFRs Table 3-7 — I/O Port SFRs Table 3-8 — Serial I/O SFRs Table 3-9 — Timer/Counter and Watchdog Timer SFRs Table 3-10 — Programmable Counter Array (PCA) SFRs Table 3-6.
ADDRESS SPACES Table 3-8. Serial I/O SFRs Mnemonic Name Address SCON Serial Control S:98H SBUF Serial Data Buffer S:99H SADEN Slave Address Mask S:B9H SADDR Slave Address S:A9H Table 3-9.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 3-10.
4 Device Configuration
CHAPTER 4 DEVICE CONFIGURATION The 8XC251Sx provides user design flexibility by configuring certain operating features at device reset.
8XC251SA, SB, SP, SQ USER’S MANUAL For ROM/OTPROM/EPROM devices, user configuration bytes UCONFIG0 and UCONFIG1 can be programmed at the factory or on-site using the procedures provided in Chapter 14, “Programming and Verifying Nonvolatile Memory.” For devices without ROM/OTPROM/ EPROM, the designer should store configuration information in an eight-byte configuration array located at the highest addresses implemented in external code memory. See Table 4-1 and Figure 4-2.
DEVICE CONFIGURATION 16 Kbytes 8 Kbytes 1:FFF9H 1:FFF8H 128 Kbytes 3:FFF9H 3:FFF8H 64 Kbytes FFF9H FFF8H 7FF9H 7FF8H 3FF9H 3FF8H 1FF9H 1FF8H 32 Kbytes 256 Kbytes x:xFFFH x:xFFEH x:xFFDH x:xFFCH Reserved x:xFFBH x:xFFAH x:xFF9H UCONFIG1 x:xFF8H UCONFIG0 Detail. Configuration array in external memory. This figure shows the addresses of configuration bytes UCONFIG1 and UCONFIG0 in external memory for several memory implementations.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 4-1. External Addresses for Configuration Array Size of External Address Bus (Bits) Address of Configuration Array on External Bus (2) Address of Configuration Bytes on External Bus (1) 16 FFF8H–FFFFH UCONFIG1: FFF9H UCONFIG0: FFF8H 17 1FFF8H–1FFFFH UCONFIG1: 1FFF9H UCONFIG0: 1FFF8H 18 3FFF8H–3FFFFH UCONFIG1: 3FFF9H UCONFIG0: 3FFF8H NOTES: 1.
DEVICE CONFIGURATION 4.4 CONFIGURATION BYTE LOCATION SELECTOR (UCON) The Configuration Byte Location Selector (UCON) applies only to OTPROM and EPROM products. In conjunction with EA#, UCON specifies whether the configuration array is accessed from on-chip memory or external memory. If the UCON bit is clear (e.g., UCON=0), the configuration array is fetched from on-chip nonvolatile memory at addresses FF:FFF8H to FF:FFFFH. The configuration bytes are located at locations FF:FFF8H and FF:FFF9H.
8XC251SA, SB, SP, SQ USER’S MANUAL Address:FF:FFF8H (2) UCONFIG0 (1), (3) 7 0 UCON WSA1# Bit Number Bit Mnemonic 7 UCON 87C251Sx — 6:5 WSA0# XALE# RD1 RD0 PAGE# SRC Function Configuration Byte Location Selector (OTPROM/EPROM products only): Clearing this bit causes the 8XC251Sx to fetch configuration information from on-chip memory.
DEVICE CONFIGURATION Address:FF:FFF9H (2) UCONFIG1 (1), (3) 7 0 — — Bit Number Bit Mnemonic 7:5 — 4 INTR — INTR WSB WSB1# WSB0# EMAP# Function Reserved for internal or future use. Set these bits when programming UCONFIG1. Interrupt Mode: If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the PC and PSW1). If this bit is clear, interrupts push the 2 lower bytes of the PC onto the stack. See 4.8, “Interrupt Mode (INTR).” 3 WSB 2:1 WSB1:0# Wait State B.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 4-2. Memory Signal Selections (RD1:0) RD1:0 P1.7/CEX/ A17/WCLK P3.7/RD#/A16 PSEN# WR# Features 0 0 A17 A16 Asserted for all addresses Asserted for writes to all memory locations 256-Kbyte external memory 0 1 P1.7/CEX4/ WCLK A16 Asserted for all addresses Asserted for writes to all memory locations 128-Kbyte external memory 1 0 P1.7/CEX4/ WCLK P3.
DEVICE CONFIGURATION 4.5.2 Configuration Bits RD1:0 The RD1:0 configuration bits (UCONFIG0.3:2) determine the number of external address signals and the address ranges for asserting the read signals PSEN#/RD# and the write signal WR#. These selections offer different ways of addressing external memory. Figures 4-5 and 4-6 show how internal memory maps into external memory for the four values of RD1:0. Section 13.
8XC251SA, SB, SP, SQ USER’S MANUAL This selection provides a 128-Kbyte external address space. The advantage of this selection, in comparison with the 256-Kbyte external memory space with RD1:0 = 00, is the availability of pin P1.7/CEX4/A17/WCLK for general I/O, PCA I/O, and real-time wait clock output. I/O P3.7 is unavailable. All four 64-Kbyte regions are strobed by PSEN# and WR#. Sections 13.8.2 and 13.8.3 show examples of memory designs with this option.
DEVICE CONFIGURATION RD1:0 = 10 16 external address bits: P0, P2 Internal Memory with Read/Write Signals External Memory 64 Kbytes Notes: 1. Single read signal 2. P3.7/RD#/A16 functions only as P3.7 PSEN#, WR# FF: FE: 00:, 01:, FE:, FF: PSEN#, WR# 01: 00: RD1:0 = 11 16 external address bits: P0, P2 Note: 1. Compatible with MCS® 51 microcontrollers 2.
8XC251SA, SB, SP, SQ USER’S MANUAL 4.5.2.3 RD1:0 = 10 (16 External Address Bits) For RD1:0 = 10, the 16 external address bits (A15:0 on ports P0 and P2) provide a single 64Kbyte region in external memory (top of Figure 4-6). This selection provides the smallest external memory space; however, pin P3.7/RD#/A16 is available for general I/O and pin P1.7/CEX4/A17/WCLK is available for general I/O, PCA I/O, and real-time wait clock output.
DEVICE CONFIGURATION 4.5.3.3 Configuration Bit XALE# Clearing XALE# (UCONFIG0.4) extends the time ALE is asserted from TOSC to 3TOSC. This accommodates an address latch that is too slow for the normal ALE signal. Section 13.4.2, “Extending ALE,” shows an external bus cycle with ALE extended. Table 4-3. RD#, WR#, PSEN# External Wait States 8XC251Sx 4.
8XC251SA, SB, SP, SQ USER’S MANUAL Figure 4-7 shows the opcode map for binary mode. Area I (columns 1 through 5 in Table A-6 on page A-4) and area II (columns 6 through F) make up the opcode map for the instructions that originate in the MCS 51 architecture. Area III in Figure 4-7 represents the opcode map for the instructions that are unique to the MCS 251 architecture (Table A-7 on page A-5). Note that some of these opcodes are reserved for future instructions.
DEVICE CONFIGURATION A5H Prefix 0H 5H 6H 6H FH FH 0H 0H I II III FH FH MCS® 51 Architecture MCS 251 Architecture MCS 51 Architecture A4131-01 Figure 4-7. Binary Mode Opcode Map A5H Prefix 0H 5H 6H 6H FH FH 0H 0H I III II FH FH MCS® 51 Architecture MCS 251 Architecture MCS 51 Architecture A4130-01 Figure 4-8.
8XC251SA, SB, SP, SQ USER’S MANUAL 4.7 MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#) For devices with 16 Kbytes of on-chip code memory (87C251SB, SQ and 83C251SB, SQ), the EMAP# bit (UCONFIG1.0) provides the option of accessing the upper half of on-chip code memory as data memory. This allows code constants to be accessed as data in region 00: using direct addressing. See section 3.2.2.
5 Programming
CHAPTER 5 PROGRAMMING The instruction set for the MCS® 251 architecture is a superset of the instruction set for the MCS® 51 architecture. This chapter describes the addressing modes and summarizes the instruction set, which is divided into data instructions, bit instructions, and control instructions. Appendix A, “Instruction Set Reference,” contains an opcode map and a detailed description of each instruction. The program status words PSW and PSW1 are also described.
8XC251SA, SB, SP, SQ USER’S MANUAL 5.2.1 Data Types Table 5-1 lists the data types that are addressed by the instruction set. Words or dwords (double words) can be in stored memory starting at any byte address; alignment on two-byte or four-byte boundaries is not required. Words and dwords are stored in memory and the register file in big endien form. Table 5-1. Data Types Data Type Bit 5.2.1.
PROGRAMMING Memory 200H 201H 202H A3H B6H 203H MOV WR0,#A3B6H MOV 00:0201H,WR0 MOV DR4,#0000C4D7H Register File 1 0 A3H 2 4 5 6 7 00H 00H C4H D7H 3 B6H DR4 WR0 Contents of register file and memory after execution A4242-01 Figure 5-1. Word and Double-word Storage in Big Endien Form Table 5-2.
8XC251SA, SB, SP, SQ USER’S MANUAL 5.2.4 Addressing Modes The MCS 251 architecture supports the following addressing modes: • • • • • register addressing: The instruction specifies the register that contains the operand. immediate addressing: The instruction contains the operand. direct addressing: The instruction contains the operand address. indirect addressing: The instruction specifies the register that contains the operand address.
PROGRAMMING 5.3.1.1 Register Addressing Both architectures address registers directly. • MCS 251 architecture. In the register addressing mode, the operand(s) in a data instruction are in byte registers (R0–R15), word registers (WR0, WR2, ..., WR30), or dword registers (DR0, DR4, ..., DR28, DR56, DR60). • MCS 51 architecture. Instructions address registers R0–R7 only. 5.3.1.2 Immediate Both architectures use immediate addressing. • MCS 251 architecture.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 5-3. Addressing Modes for Data Instructions in the MCS® 51 Architecture Mode Address Range of Operand Assembly Language Reference Comments Register 00H–1FH R0–R7 (Bank selected by PSW) Immediate Operand in Instruction #data = #00H–#FFH 00H–7FH dir8 = 00H–7FH On-chip RAM SFRs dir8 = 80H–FFH or SFR mnemonic. SFR address 00H–FFH @R0, @R1 Accesses on-chip RAM or the lowest 256 bytes of external data memory (MOVX).
PROGRAMMING Table 5-4. Addressing Modes for Data Instructions in the MCS® 251 Architecture Mode Address Range of Operand Assembly Language Notation Comments R0–R15, WR0–WR30, DR0–DR28, DR56, DR60 R0–R7, WR0–WR6, DR0, and DR2 are in the register bank currently selected by the PSW and PSW1. N.A. (Operand is in the instruction) #short = 1, 2, or 4 Used only in increment and decrement instructions. Immediate, 8 bits N.A. (Operand is in the instruction) #data8 = #00H–#FFH Immediate, 16 bits N.A.
8XC251SA, SB, SP, SQ USER’S MANUAL 5.3.1.5 Displacement Several move instructions use displacement addressing to move bytes or words from a source to a destination. Sixteen-bit displacement addressing (@WRj+dis16) accesses indirectly the lowest 64 Kbytes in memory. The base address can be in any word register WRj. The instruction contains a 16-bit signed offset which is added to the base address. Only the lowest 16 bits of the sum are used to compute the operand address.
PROGRAMMING The MCS 251 architecture provides the MUL (multiply) and DIV (divide) instructions for unsigned 8-bit and 16-bit data (Table A-22 on page A-16). Signed multiply and divide are left for the user to manage through a conversion process.
8XC251SA, SB, SP, SQ USER’S MANUAL 5.3.4 Data Transfer Instructions Data transfer instructions copy data from one register or memory location to another. These instructions include the move instructions (Table A-24 on page A-19) and the exchange, push, and pop instructions (Table A-25 on page A-22). Instructions that move only a single bit are listed with the other bit instructions in Table A-26 on page A-23.
PROGRAMMING 5.4 BIT INSTRUCTIONS A bit instruction addresses a specific bit in a memory location or SFR. There are four categories of bit instructions: • SETB (Set Bit), CLR (Clear Bit), CPL (Complement Bit). These instructions can set, clear or complement any addressable bit. • ANL (And Logical), ANL/ (And Logical Complement), ORL (OR Logical), ORL/ (Or Logical Complement). These instructions allow ANDing and ORing of any addressable bit or its complement with the CY flag.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 5-7 lists the addressing modes for bit instructions and Table A-26 on page A-23 summarizes the bit instructions. “Bit” denotes a bit that is addressed by a new instruction in the MCS 251 architecture and “bit51” denotes a bit that is addressed by an instruction in the MCS 51 architecture. Table 5-6. Addressing Two Sample Bits Addressing Mode Location On-chip RAM SFR MCS® 51 Architecture MCS 251 Architecture Register Name RAMREG.5 RAMREG.
PROGRAMMING 5.5.1 Addressing Modes for Control Instructions Table 5-8 lists the addressing modes for the control instructions. • Relative addressing: The control instruction provides the target address as an 8-bit signed offset (rel) from the address of the next instruction. • Direct addressing: The control instruction provides a target address, which can have 11 bits (addr11), 16 bits (addr16), or 24 bits (addr24). The target address is written to the PC.
8XC251SA, SB, SP, SQ USER’S MANUAL 5.5.2 Conditional Jumps The MCS 251 architecture supports bit-conditional jumps, compare-conditional jumps, and jumps based on the value of the accumulator. A bit-conditional jump is based on the state of a bit. In a compare-conditional jump, the jump is based on a comparison of two operands. All conditional jumps are relative, and the target address (rel) must be in the current 256-byte block of code.
PROGRAMMING 5.5.3 Unconditional Jumps There are five unconditional jumps. NOP and SJMP jump to addresses relative to the program counter. AJMP, LJMP, and EJMP jump to direct or indirect addresses. • NOP (No Operation) is an unconditional jump to the next instruction. • SJMP (Short Jump) jumps to any instruction within -128 to 127 of the next instruction. • AJMP (Absolute Jump) changes the lowest 11 bits of the PC to jump anywhere within the current 2-Kbyte block of memory.
8XC251SA, SB, SP, SQ USER’S MANUAL RETI (Return from Interrupt) provides a return from an interrupt service routine. The operation of RETI depends on the INTR bit in the UCONFIG1 or CONFIG1 configuration byte: • For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the following order: PC.7:0, PC.15:8. The RETI instruction pops these two bytes and uses them as the 16-bit return address in region FF:.
PROGRAMMING Table 5-10. The Effects of Instructions on the PSW and PSW1 Flags Flags Affected (1), (5) Instruction Type Instruction CY OV AC (2) N Z X X X X X MUL, DIV (3) 0 X DA X ADD, ADDC, SUB, SUBB, CMP Arithmetic Logical Program Control INC, DEC ANL, ORL, XRL, CLR A, CPL A, RL, RR, SWAP X X X X X X X X RLC, RRC, SRL, SLL, SRA (4) X X X CJNE X X X X X DJNE NOTES: 1. X = the flag can be affected by the instruction. 0 = the flag is cleared by the instruction. 2.
8XC251SA, SB, SP, SQ USER’S MANUAL . Address: Reset State: PSW S:D0H 0000 0000B 7 0 CY Bit Number 7 AC F0 RS1 RS0 Bit Mnemonic CY OV UD P Function Carry Flag: The carry flag is set by an addition instruction (ADD, ADDC) if there is a carry out of the MSB. It is set by a subtraction (SUB, SUBB) or compare (CMP) if a borrow is needed for the MSB.
PROGRAMMING . Address: Reset State: PSW1 S:D1H 0000 0000B 7 0 CY AC Bit Number N RS1 Bit Mnemonic RS0 OV Z — Function 7 CY Carry Flag: 6 AC Auxiliary Carry Flag: Identical to the CY bit in the PSW register (Figure 5-2). Identical to the AC bit in the PSW register (Figure 5-2). 5 N Negative Flag: This bit is set if the result of the last logical or arithmetic operation was negative (i.e., bit 15 = 1). Otherwise it is cleared.
6 Interrupt System
CHAPTER 6 INTERRUPT SYSTEM 6.1 OVERVIEW The 8XC251Sx, like other control-oriented computer architectures, employs a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal 8XC251Sx activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g.
8XC251SA, SB, SP, SQ USER’S MANUAL Interrupt Enable EA Priority Enable Highest Priority Interrupt IP 0 IE0 IT0 INT0# EX0 1 Timer 0 TF0 ET0 0 IE1 IT1 EX1 1 Timer 1 TF1 ET1 PCA Counter Overflow PCA Match or Capture 0 ECF CF 1 0 ECCFx 5 CCFx 1 Receive RI Transmit TI Timer 2 TF2 T2EX Interrupt Polling Sequence INT1# EC ES EXF2 ET2 Lowest Priority Interrupt A4149-01 Figure 6-1.
INTERRUPT SYSTEM Table 6-2. Interrupt System Special Function Registers Mnemonic Description Address IE0 Interrupt Enable Register. Used to enable and disable programmable interrupts. The reset value of this register is zero (interrupts disabled). S:A8H IPL0 Interrupt Priority Low Register. Establishes relative four-level priority for programmable interrupts. Used in conjunction with IPH0. S:B8H IPH0 Interrupt Priority High Register.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 6-3. Interrupt Control Matrix Global Enable PCA Timer 2 Serial Port Timer 1 INT1# Timer 0 INT0# Bit Name in IE0 Register EA EC ET2 ES ET1 EX1 ET0 EX0 Interrupt PriorityWithin-Level (7 = Low Priority, 1 = High Priority) NA 7 6 5 4 3 2 1 Reserved Reserved IPH0.6 IPL0.6 IPH0.5 IPL0.5 IPH0.4 IPL0.4 IPH0.3 IPL0.3 IPH0.2 IPL0.2 IPH0.1 IPL0.1 IPH0.0 IPL0.
INTERRUPT SYSTEM 6.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT The programmable counter array (PCA) interrupt is generated by the logical OR of five event flags (CCFx) and the PCA timer overflow flag (CF) in the CCON register (see Figure 9-8 on page 9-14). All PCA interrupts share a common interrupt vector. Bits are not cleared by hardware vectors to service routines. Normally, interrupt service routines resolve interrupt requests and clear flag bits.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: IE0 S:A8H 0000 0000B 7 0 EA Bit Number 7 EC ET2 ES ET1 Bit Mnemonic EA EX1 ET0 EX0 Function Global Interrupt Enable: Setting this bit enables all interrupts that are individually enabled by bits 0–6. Clearing this bit disables all interrupts, except the TRAP interrupt, which is always enabled. 6 EC 5 ET2 PCA Interrupt Enable: Setting this bit enables the PCA interrupt.
INTERRUPT SYSTEM 6.6 INTERRUPT PRIORITIES Each of the seven 8XC251Sx interrupt sources may be individually programmed to one of four priority levels. This is accomplished with the IPH0.x/IPL0.x bit pairs in the interrupt priority high (IPH0) and interrupt priority low (IPL0) registers (Figures 6-3 and 6-4 on page 6-8). Specify the priority level as shown in Table 6-4 using IPH0.x as the MSB and IPL0.x as the LSB. Table 6-4. Level of Priority IPH0.x (MSB) IPL0.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: IPH0 S:B7H X000 0000B 7 0 — Bit Number IPH0.6 IPH0.5 IPH0.4 IPH0.3 Bit Mnemonic IPH0.2 IPH0.1 IPH0.0 Function 7 — Reserved. The value read from this bit is indeterminate. Write a “0” to this bit. 6 IPH0.6 PCA Interrupt Priority Bit High 5 IPH0.5 Timer 2 Overflow Interrupt Priority Bit High 4 IPH0.4 Serial I/O Port Interrupt Priority Bit High 3 IPH0.3 Timer 1 Overflow Interrupt Priority Bit High 2 IPH0.
INTERRUPT SYSTEM 6.7 INTERRUPT PROCESSING Interrupt processing is a dynamic operation that begins when a source requests an interrupt and lasts until the execution of the first instruction in the interrupt service routine (see Figure 6-5). Response time is the amount of time between the interrupt request and the resulting break in the current instruction stream. Latency is the amount of time between the interrupt request and the execution of the first instruction in the interrupt service routine.
8XC251SA, SB, SP, SQ USER’S MANUAL 6.7.1 Minimum Fixed Interrupt Time All interrupts are sampled or polled every four state times (see Figure 6-5). Two of eight interrupts are latched and polled per state time within any given four state time window. One additional state time is required for a context switch request. For code branches to jump locations in the current 64-Kbyte memory region (compatible with MCS 51 microcontrollers), the context switch time is 11 states.
INTERRUPT SYSTEM time is five states for internal interrupts and six states for external interrupts. External interrupts must remain active for at least five state times to guarantee interrupt recognition when the request occurs immediately after a sample has been taken (i.e., requested in the second half of a sample state time). If the external interrupt goes active one state after the sample state, the pin is not resampled for another three states.
8XC251SA, SB, SP, SQ USER’S MANUAL Response Time = 4 OSC State Time INT0# Sample INT0# Request Ten State Instruction Push PC A4154-02 Figure 6-7. Response Time Example #2 6.7.2.2 Computation of Worst-case Latency With Variables Worst-case latency calculations assume that the longest 8XC251Sx instruction used in the program must fully execute prior to a context switch.
INTERRUPT SYSTEM Table 6-6. Interrupt Latency Variables Variable INT0#, INT1#, T2EX External Execution Page Mode >64K Jump to ISR (1) External Memory Wait State External Stack <64K (1) External Stack >64K (1) External Stack Wait State Number of States Added 1 2 1 8 1 per bus cycle 4 8 1 per bus cycle NOTES: 1. <64K/>64K means inside/outside the 64-Kbyte memory region where code is executing. 2. Base-case fixed time is 16 states and assumes: — A 2-byte instruction is the first ISR byte.
8XC251SA, SB, SP, SQ USER’S MANUAL 6.7.2.4 Blocking Conditions If all enable and priority requirements have been met, a single prioritized interrupt request at a time generates a vector cycle to an interrupt service routine (refer to the CALL instructions in Appendix A, “Instruction Set Reference”). There are three causes of blocking conditions with hardware-generated vectors: 1.
INTERRUPT SYSTEM 6.7.3 ISRs in Process ISR execution proceeds until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is completed. The RETI instruction in the ISR pops PC address bytes off the stack (as well as PSW1 for INTR = 1) and execution resumes at the suspended instruction stream. NOTE Some programs written for MCS 51 microcontrollers use RETI instead of RET to return from a subroutine that is called by ACALL or LCALL (i.e.
7 Input/Output Ports
CHAPTER 7 INPUT/OUTPUT PORTS 7.1 INPUT/OUTPUT PORT OVERVIEW The 8XC251Sx uses input/output (I/O) ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations (see Chapter 13, “External Memory Interface”); others allow for alternate functions. All four 8XC251Sx I/O ports are bidirectional. Each port contains a latch, an output driver, and an input buffer.
8XC251SA, SB, SP, SQ USER’S MANUAL 7.2 I/O CONFIGURATIONS Each port SFR operates via type-D latches, as illustrated in Figure 7-1 for ports 1 and 3. A CPU “write to latch” signal initiates transfer of internal bus data into the type-D latch. A CPU “read latch” signal transfers the latched Q output onto the internal bus. Similarly, a “read pin” signal transfers the logical level of the port pin. Some port data instructions activate the “read latch” signal while others activate the “read pin” signal.
INPUT/OUTPUT PORTS VCC Alternate Output Function Read Latch Internal Pullup P3.x Internal Bus D Write to Latch CL P3.x Latch Q Q# Read Pin Alternate Input Function A2239-01 Figure 7-1. Port 1 and Port 3 Structure Address/ Data Read Latch Control VCC P0.x Internal Bus Write to Latch D CL P0.x Latch Q 1 Q# 0 Read Pin A2238-01 Figure 7-2.
8XC251SA, SB, SP, SQ USER’S MANUAL VCC Address Control Internal Pullup Read Latch 1 Internal Bus D Write to Latch CL P2.x 0 Q P2.x Latch Q# Read Pin A2240-01 Figure 7-3. Port 2 Structure When port 0 and port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line. Section 7.8, “External Memory Access,” discusses the operation of port 0 and port 2 as the external address/data bus.
INPUT/OUTPUT PORTS 7.5 READ-MODIFY-WRITE INSTRUCTIONS Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data, and then rewrite the latch. These are called “read-modify-write” instructions. Below is a complete list of these special instructions. When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin: ANL (logical AND, e.g., ANL P1, A) ORL (logical OR, e.g.
8XC251SA, SB, SP, SQ USER’S MANUAL 7.6 QUASI-BIDIRECTIONAL PORT OPERATION Port 1, port 2, and port 3 have fixed internal pullups and are referred to as “quasi-bidirectional” ports. When configured as an input, the pin impedance appears as logic one and sources current (see the 8XC251Sx datasheet) in response to an external logic-zero condition. Port 0 is a “true bidirectional” pin. The pin floats when configured as input. Resets write logical one to all port latches.
INPUT/OUTPUT PORTS 2 Osc. Periods VCC VCC P1 P2 VCC P3 Port Q# From Port Latch n Input Data Read Port Pin A2242-01 Figure 7-4. Internal Pullup Configurations 7.7 PORT LOADING Output buffers of port 1, port 2, and port 3 can each sink 1.6 mA at logic zero (see VOL specifications in the 8XC251Sx data sheet). These port pins can be driven by open-collector and opendrain devices. Logic zero-to-one transitions occur slowly as limited current pulls the pin to a logic-one condition (Figure 7-4).
8XC251SA, SB, SP, SQ USER’S MANUAL The 8XC251Sx CPU writes FFH to the P0 register for all external memory bus cycles. This overwrites previous information in P0. In contrast, the P2 register is unmodified for external bus cycles. When address bits or data bits are not on the port 2 pins, the bit values in P2 appear on the port 2 pins. In nonpage mode, port 0 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the lower address byte and the data.
INPUT/OUTPUT PORTS Table 7-2. Instructions for External Data Moves Bus Width Instructions 8 MOVX @Ri; MOV @Rm; MOV dir8 16 MOVX @DPTR; MOV @WRj; MOV @WRj+dis; MOV dir16 17 MOV @DRk; MOV @DRk+dis 18 MOV @DRk; MOV @DRk+dis NOTE Avoid MOV P0 instructions for external memory accesses. These instructions can corrupt input code bytes at port 0. External signal ALE (address latch enable) facilitates external address latch capture. The address byte is valid after the ALE pin drives VOL.
8 Timer/Counters and Watchdog Timer
CHAPTER 8 TIMER/COUNTERS AND WATCHDOG TIMER This chapter describes the timer/counters and the watchdog timer (WDT) included as peripherals on the 8XC251Sx. When operating as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. When operating as a counter, a timer/counter counts negative transitions on an external pin. After a preset number of counts, the counter issues an interrupt request. Timer/counters are covered in sections 8.1 through 8.6.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 8-1. Timer/Counter and Watchdog Timer SFRs Mnemonic Description Address TL0 TH0 Timer 0 Timer Registers. Used separately as 8-bit counters or in cascade as a 16-bit counter. Counts an internal clock signal with frequency FOSC/12 (timer operation) or an external input (event counter operation). S:8AH S:8CH TL1 TH1 Timer 1 Timer Registers. Used separately as 8-bit counters or in cascade as a 16-bit counter.
TIMER/COUNTERS AND WATCHDOG TIMER For timer operation (C/Tx# = 0), the timer register counts the divided-down system clock. The timer register is incremented once every peripheral cycle, i.e., once every six states (see section 2.2.2, “Clock and Reset Unit”). Since six states equals 12 clock cycles, the timer clock rate is FOSC/12. Exceptions are the timer 2 baud rate and clock-out modes, where the timer register is incremented by the system clock divided by two.
8XC251SA, SB, SP, SQ USER’S MANUAL For normal timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation. This setup can be used to make pulse width measurements. See section 8.5.2, “Pulse Width Measurements.” Timer 0 overflow (count rolls over from all 1s to all 0s) sets the TF0 flag generating an interrupt request. 8.3.
TIMER/COUNTERS AND WATCHDOG TIMER 8.3.3 Mode 2 (8-bit Timer With Auto-reload) Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the TH0 register (Figure 8-3). TL0 overflow sets the timer overflow flag (TF0) in the TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. See section 8.5.1, “Auto-load Setup Example.
8XC251SA, SB, SP, SQ USER’S MANUAL Timer 1 is controlled by the four high-order bits of the TMOD register (Figure 8-5) and bits 7, 6, 3, and 2 of the TCON register (Figure 8-6). The TMOD register selects the method of timer gating (GATE1), timer or counter operation (T/C1#), and mode of operation (M11 and M01). The TCON register provides timer 1 control functions: overflow flag (TF1), run control (TR1), interrupt flag (IE1), and interrupt type control (IT1).
TIMER/COUNTERS AND WATCHDOG TIMER Address: Reset State: TMOD S:89H 0000 0000B 7 0 GATE1 Bit Number 7 C/T1# M11 M01 GATE0 Bit Mnemonic GATE1 C/T0# M10 M00 Function Timer 1 Gate: When GATE1 = 0, run control bit TR1 gates the input signal to the timer register. When GATE1 = 1 and TR1 = 1, external signal INT1 gates the timer input. 6 C/T1# Timer 1 Counter/Timer Select: C/T1# = 0 selects timer operation: timer 1 counts the divided-down system clock.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: TCON S:88H 0000 0000B 7 0 TF1 Bit Number 7 TR1 TF0 TR0 IE1 Bit Mnemonic TF1 IT1 IE0 IT0 Function Timer 1 Overflow Flag: Set by hardware when the timer 1 register overflows. Cleared by hardware when the processor vectors to the interrupt routine. 6 TR1 Timer 1 Run Control Bit: 5 TF0 Timer 0 Overflow Flag: Set/cleared by software to turn timer 1 on/off. Set by hardware when the timer 0 register overflows.
TIMER/COUNTERS AND WATCHDOG TIMER 8.4.1 Mode 0 (13-bit Timer) Mode 0 configures timer 0 as a 13-bit timer, which is set up as an 8-bit timer (TH1 register) with a modulo-32 prescalar implemented with the lower 5 bits of the TL1 register (Figure 8-2). The upper 3 bits of the TL1 register are ignored. Prescalar overflow increments the TH1 register. 8.4.2 Mode 1 (16-bit Timer) Mode 1 configures timer 1 as a 16-bit timer with TH1 and TL1 connected in cascade (Figure 8-2). The selected input increments TL1.
8XC251SA, SB, SP, SQ USER’S MANUAL 3. Enter an eight-bit reload value (nR) in register TH0. This can be the same as n0 or different, depending on the application. 4. Set the TR0 bit in the TCON register (Figure 8-6) to start the timer. Timer overflow occurs after FFH + 1 - n0 peripheral cycles, setting the TF0 flag and loading nR into TL0 from TH0. When the interrupt is serviced, hardware clears TF0. 5.
TIMER/COUNTERS AND WATCHDOG TIMER Timer 2 provides the following operating modes: capture mode, auto-reload mode, baud rate generator mode, and programmable clock-out mode. Select the operating mode with T2MOD and TCON register bits as shown in Table 8-3 on page 8-15. Auto-reload is the default mode. Setting RCLK and/or TCLK selects the baud rate generator mode. Timer 2 operation is similar to timer 0 and timer 1.
8XC251SA, SB, SP, SQ USER’S MANUAL 8.6.2 Auto-reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. The timer operates an as an up counter or as an up/down counter, as determined by the down counter enable bit (DCEN). At device reset, DCEN is cleared, so in the auto-reload mode, timer 2 defaults to operation as an up counter. 8.6.2.1 Up Counter Operation When DCEN = 0, timer 2 operates as an up counter (Figure 8-8).
TIMER/COUNTERS AND WATCHDOG TIMER 8.6.2.2 Up/Down Counter Operation When DCEN = 1, timer 2 operates as an up/down counter (Figure 8-9). External pin T2EX controls the direction of the count (Table 8-2 on page 8-3). When T2EX is high, timer 2 counts up. The timer overflow occurs at FFFFH which sets the timer 2 overflow flag (TF2) and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L to be loaded into the timer registers TH2 and TL2.
8XC251SA, SB, SP, SQ USER’S MANUAL 8.6.3 Baud Rate Generator Mode This mode configures timer 2 as a baud rate generator for use with the serial port. Select this mode by setting the RCLK and/or TCLK bits in T2CON. See Table 8-3. For details regarding this mode of operation, refer to section 10.6, “Baud Rates.” 8.6.4 Clock-out Mode In the clock-out mode, timer 2 functions as a 50%-duty-cycle, variable-frequency clock (Figure 8-10). The input clock increments TL0 at frequency FOSC/2.
TIMER/COUNTERS AND WATCHDOG TIMER XTAL1 0 2 TL2 (8 Bits) TH2 (8 Bits) 1 T2 TR2 RCAP2H RCAP2L C/T2# 2 T2OE T2EX Interrupt Request EXF2 EXEN2 A4116-02 Figure 8-10. Timer 2: Clock Out Mode . Table 8-3.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: T2MOD S:C9H XXXX XX00B 7 0 — — Bit Number 7:2 — — Bit Mnemonic — — — T2OE DCEN Function Reserved: The values read from these bits are indeterminate. Write zeros to these bits. 1 T2OE Timer 2 Output Enable Bit: In the timer 2 clock-out mode, connects the programmable clock output to external pin T2. 0 DCEN Down Count Enable Bit: Configures timer 2 as an up/down counter. Figure 8-11. T2MOD: Timer 2 Mode Control Register 8.
TIMER/COUNTERS AND WATCHDOG TIMER Address: Reset State: T2CON S:C8H 0000 0000B 7 0 TF2 Bit Number 7 EXF2 RCLK TCLK EXEN2 Bit Mnemonic TF2 TR2 C/T2# CP/RL2# Function Timer 2 Overflow Flag: Set by timer 2 overflow. Must be cleared by software. TF2 is not set if RCLK = 1 or TCLK = 1. 6 EXF2 Timer 2 External Flag: If EXEN2 = 1, capture or reload caused by a negative transition on T2EX sets EFX2. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
8XC251SA, SB, SP, SQ USER’S MANUAL 8.7.2 Using the WDT To use the WDT to recover from software malfunctions, the user program should control the WDT as follows: 1. Following device reset, write the two-byte sequence 1EH-E1H to the WDTRST register to enable the WDT. The WDT begins counting from 0. 2. Repeatedly for the duration of program execution, write the two-byte sequence 1EH-E1H to the WDTRST register to clear and enable the WDT before it overflows. The WDT starts over at 0.
9 Programmable Counter Array
CHAPTER 9 PROGRAMMABLE COUNTER ARRAY This chapter describes the programmable counter array (PCA), an on-chip peripheral of the 8XC251Sx that performs a variety of timing and counting operations, including pulse width modulation (PWM). The PCA provides the capability for a software watchdog timer (WDT). 9.1 PCA DESCRIPTION The programmable counter array (PCA) consists of a 16-bit timer/counter and five 16-bit compare/capture modules.
8XC251SA, SB, SP, SQ USER’S MANUAL 9.1.1 Alternate Port Usage PCA modules 3 and 4 share port pins with the real-time wait state and address functions as follows: • PCA module 3 — P1.6/CEX3/WAIT# • PCA module 4 — P1.7/CEX4/A17/WCLK When the real-time wait state functions are enabled (using the WCON register), the corresponding PCA modules are automatically disabled. Configuring the 8XC251Sx to use address line A17 (specified by UCONFIG0, bits RD1:0) overrides the PCA module 3 and WCLK functions.
i_pca.fm5 Page 3 Thursday, June 27, 1996 1:39 PM PROGRAMMABLE COUNTER ARRAY Setting the run control bit (CR in the CCON register) turns the PCA timer/counter on, if the output of the NAND gate (Figure 9-1) equals logic 1. The PCA timer/counter continues to operate during idle mode unless the CIDL bit of the CMOD register is set. The CPU can read the contents of the CH and CL registers at any time. However, writing to them is inhibited while they are counting (i.e., when the CR bit is set).
8XC251SA, SB, SP, SQ USER’S MANUAL Table 9-1. PCA Special Function Registers (SFRs) Mnemonic Description Address CL CH PCA Timer/Counter. These registers serve as a common 16-bit timer or event counter for the five compare/capture modules. Counts FOSC/12, FOSC/4, timer 0 overflow, or the external signal on P1.2/ECI, as selected by CMOD. In PWM mode CL operates as an 8-bit timer. S:E9H S:F9H CCON PCA Timer/Counter Control Register.
PROGRAMMABLE COUNTER ARRAY 9.3 PCA COMPARE/CAPTURE MODULES Each compare/capture module is made up of a compare/capture register pair (CCAPxH/CCAPxL), a 16-bit comparator, and various logic gates and signal transition selectors. The registers store the time or count at which an external event occurred (capture) or at which an action should occur (comparison). In the PWM mode, the low-byte register controls the duty cycle of the output waveform.
8XC251SA, SB, SP, SQ USER’S MANUAL To program a compare/capture module for the 16-bit capture mode, program the CAPPx and CAPNx bits in the module’s CCAPMx register as follows: • To trigger the capture on a positive transition, set CAPPx and clear CAPNx. • To trigger the capture on a negative transition, set CAPNx and clear CAPPx. • To trigger the capture on a positive or negative transition, set both CAPPx and CAPNx. Table 9-3 on page 9-14 lists the bit combinations for selecting module modes.
PROGRAMMABLE COUNTER ARRAY 9.3.2 Compare Modes The compare function provides the capability for operating the five modules as timers, event counters, or pulse width modulators. Four modes employ the compare function: 16-bit software timer mode, high-speed output mode, WDT mode, and PWM mode. In the first three of these, the compare/capture module continuously compares the 16-bit PCA timer/counter value with the 16bit value pre-loaded into the module’s CCAPxH/CCAPxL register pair.
8XC251SA, SB, SP, SQ USER’S MANUAL PCA Timer/Counter Count Input CH (8 Bits) CL (8 Bits) Compare/Capture Module CCAPx H CCAPx L (8 Bits) (8 Bits) Toggle Match 16-Bit Comparator CEXx Interrupt Request Enable CCFx Enable CCON X ECOMx 0 7 0 MATx TOGx CCAPMx Mode Register 0 ECCFx 0 "0" Reset Write to CCAPx L "1" Write to CCAPx H X = Don't Care x = 0, 1, 2, 3, 4 For software timer mode, set ECOMx and MATx. For high speed output mode, set ECOMx, MATx, and TOGx. A4164-01 Figure 9-3.
PROGRAMMABLE COUNTER ARRAY The user also has the option of generating an interrupt request when the match occurs by setting the corresponding interrupt enable bit (ECCFx in the CCAPMx register). Since hardware does not clear the compare/capture flag when the interrupt is processed, the user must clear the flag in software.
8XC251SA, SB, SP, SQ USER’S MANUAL The PCA WDT generates a reset signal each time a match occurs.
PROGRAMMABLE COUNTER ARRAY 9.3.6 Pulse Width Modulation Mode The five PCA comparator/capture modules can be independently programmed to function as pulse width modulators (Figure 9-5). The modulated output, which has a pulse width resolution of eight bits, is available at the CEXx pin. The PWM output can be used to convert digital data to an analog signal with simple external circuitry.
8XC251SA, SB, SP, SQ USER’S MANUAL The value in CCAPxL determines the duty cycle of the current period. The value in CCAPxH determines the duty cycle of the following period. Changing the value in CCAPxL over time modulates the pulse width. As depicted in Figure 9-6, the 8-bit value in CCAPxL can vary from 0 (100% duty cycle) to 255 (0.4% duty cycle). NOTE To change the value in CCAPxL without glitches, write the new value to the high byte register (CCAPxH).
PROGRAMMABLE COUNTER ARRAY Address: Reset State: CMOD S:D9H 00XX X000B 7 0 CIDL Bit Number 7 WDTE — — Bit Mnemonic CIDL — CPS1 CPS0 ECF Function PCA Timer/Counter Idle Control: CIDL = 1 disables the PCA timer/counter during idle mode. CIDL = 0 allows the PCA timer/counter to run during idle mode. 6 WDTE Watchdog Timer Enable: WDTE = 1 enables the watchdog timer output on PCA module 4. WDTE = 0 disables the PCA watchdog timer output.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: CCON S:D8H 00X0 0000B 7 0 CF CR Bit Number — CCF4 CCF3 Bit Mnemonic 7 CF CCF2 CCF1 CCF0 Function PCA Timer/Counter Overflow Flag: Set by hardware when the PCA timer/counter rolls over. This generates an interrupt request if the ECF interrupt enable bit in CMOD is set. CF can be set by hardware or software but can be cleared only by software.
PROGRAMMABLE COUNTER ARRAY Address: CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 CCAPMx (x = 0–4) S:DAH S:DBH S:DCH S:DDH S:DEH Reset State: X000 0000B 7 0 ECOMx — Bit Number 7 CAPPx CAPNx MATx Bit Mnemonic — TOGx PWMx ECCFx Function Reserved: The value read from this bit is indeterminate. Write a zero to this bit. 6 ECOMx Compare Modes: ECOMx = 1 enables the module comparator function.
10 Serial I/O Port
CHAPTER 10 SERIAL I/O PORT The serial input/output port supports communication with modems and other external peripheral devices. This chapter provides instructions for programming the serial port and generating the serial I/O baud rates with timer 1 and timer 2. 10.1 OVERVIEW The serial I/O port provides both synchronous and asynchronous communication modes. It operates as a universal asynchronous receiver and transmitter (UART) in three full-duplex modes (modes 1, 2, and 3).
8XC251SA, SB, SP, SQ USER’S MANUAL Table 10-2. Serial Port Special Function Registers Mnemonic Description Address SBUF Serial Buffer. Two separate registers comprise the SBUF register. Writing to SBUF loads the transmit buffer; reading SBUF accesses the receive buffer. 99H SCON Serial Port Control. Selects the serial port operating mode.
SERIAL I/O PORT The serial port control (SCON) register (Figure 10-2) configures and controls the serial port. Address: Reset State: SCON 98H 0000 0000B 7 0 FE/SM0 Bit Number 7 SM1 SM2 REN Bit Mnemonic FE TB8 RB8 TI RI Function Framing Error Bit: To select this function, set the SMOD0 bit in the PCON register. Set by hardware to indicate an invalid stop bit. Cleared by software, not by valid frames.
8XC251SA, SB, SP, SQ USER’S MANUAL 1 TI Transmit Interrupt Flag Bit: Set by the transmitter after the last data bit is transmitted. Cleared by software. 0 RI Receive Interrupt Flag Bit: Set by the receiver after the last data bit of a frame has been received. Cleared by software. Figure 10-2. SCON: Serial Port Control Register (Continued) 10.2 MODES OF OPERATION The serial I/O port can operate in one synchronous and three asynchronous modes. 10.2.
SERIAL I/O PORT Transmit TXD S3P1 S6P1 Write to SBUF S6P2 Shift S6P2 D0 RXD S6P2 D1 D2 S6P2 D6 S6P2 D7 S6P2 S6P2 TI S1P1 Receive TXD S3P1 S6P1 Write to SCON Set REN, Clear RI S6P2 Shift S6P2 D0 S6P2 D1 S6P2 D6 S6P2 D7 RXD S6P2 S6P2 S5P2 RI S1P1 A4124-02 Figure 10-3. Mode 0 Timing 10.2.1.2 Reception (Mode 0) To start a reception in mode 0, write to the SCON register. Clear bits SM0, SM1, and RI and set the REN bit.
8XC251SA, SB, SP, SQ USER’S MANUAL 10.2.2 Asynchronous Modes (Modes 1, 2, and 3) The serial port has three asynchronous modes of operation. • Mode 1. Mode 1 is a full-duplex, asynchronous mode. The data frame (Figure 10-4) consists of 10 bits: one start bit, eight data bits, and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. When a message is received, the stop bit is read in the RB8 bit in the SCON register.
SERIAL I/O PORT 10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3) Framing bit error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set the SMOD0 bit in the PCON register (Figure 12-1 on page 12-2). When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs.
8XC251SA, SB, SP, SQ USER’S MANUAL Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address does the receiver set the RI bit in the SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices.
SERIAL I/O PORT The SADEN byte is selected so that each slave may be addressed separately. For Slave A, bit 0 (the LSB) is a don't-care bit; for Slaves B and C, bit 0 is a 1. To communicate with Slave A only, the master must send an address where bit 0 is clear (e.g., 1111 0000). For Slave A, bit 1 is a 0; for Slaves B and C, bit 1 is a don’t-care bit. To communicate with Slaves B and C, but not Slave A, the master must send an address with bits 0 and 1 both set (e.g., 1111 0011).
8XC251SA, SB, SP, SQ USER’S MANUAL 10.5.3 Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00H, i.e., the given and broadcast addresses are XXXX XXXX (all don't-care bits). This ensures that the serial port is backwardscompatible with MCS® 51 microcontrollers that do not support automatic address recognition. 10.6 BAUD RATES You must select the baud rate for the serial port transmitter and receiver when operating in modes 1, 2, and 3. (The baud rate is preset for mode 0.
SERIAL I/O PORT 10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) Timer 1 is the default baud rate generator for the transmitter and the receiver in modes 1 and 3. The baud rate is determined by the timer 1 overflow rate and the value of SMOD, as shown in the following formula: Serial I/O Modes 1 and 3 Baud Rate = 2 10.6.3.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 10-4. Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3 Baud Rate Timer 1 SMOD1 C/T# Mode Reload Value 62.5 Kbaud (Max) 12.0 MHz 1 0 2 FFH 19.2 Kbaud 11.059 MHz 1 0 2 FDH 9.6 Kbaud 11.059 MHz 0 0 2 FDH 4.8 Kbaud 11.059 MHz 0 0 2 FAH 2.4 Kbaud 11.059 MHz 0 0 2 F4H 1.2 Kbaud 137.5 Baud 10.6.3.3 Oscillator Frequency (FOSC) 11.059 MHz 0 0 2 E8H 11.986 MHz 0 0 2 1DH 110.0 Baud 6.0 MHz 0 0 2 72H 110.0 Baud 12.
SERIAL I/O PORT You may configure timer 2 as a timer or a counter. In most applications, it is configured for timer operation (i.e., the C/T2# bit is clear in the T2CON register). Table 10-5. Selecting the Baud Rate Generator(s) RCLCK Bit TCLCK Bit Receiver Baud Rate Generator Transmitter Baud Rate Generator 0 0 Timer 1 Timer 1 0 1 Timer 1 Timer 2 1 0 Timer 2 Timer 1 1 1 Timer 2 Timer 2 Note: Oscillator frequency is divided by 2, not 12.
8XC251SA, SB, SP, SQ USER’S MANUAL Note that timer 2 increments every state time (2TOSC) when it is in the baud rate generator mode.
11 Minimum Hardware Setup
CHAPTER 11 MINIMUM HARDWARE SETUP This chapter discusses the basic operating requirements of the MCS® 251 microcontroller and describes a minimum hardware setup. Topics covered include power, ground, clock source, and device reset. For parameter values, refer to the device data sheet. 11.1 MINIMUM HARDWARE SETUP Figure 11-1 shows a minimum hardware setup that employs the on-chip oscillator for the system clock and provides power-on reset. Control signals and Ports 0, 1, 2, and 3 are not shown.
8XC251SA, SB, SP, SQ USER’S MANUAL 11.2 ELECTRICAL ENVIRONMENT The 8XC251Sx is a high-speed CHMOS device. To achieve satisfactory performance, its operating environment should accommodate the device signal waveforms without introducing distortion or noise. Design considerations relating to device performance are discussed in this section. See the device data sheet for voltage and current requirements, operating frequency, and waveform timing. 11.2.
MINIMUM HARDWARE SETUP 11.3 CLOCK SOURCES The 8XC251Sx can obtain the system clock signal from an external clock source (Figure 11-3) or it can generate the clock signal using the on-chip oscillator amplifier and external capacitors and resonator (Figure 11-2). 11.3.1 On-chip Oscillator (Crystal) This clock source uses an external quartz crystal connected from XTAL1 to XTAL2 as the frequency-determining element (Figure 11-2).
8XC251SA, SB, SP, SQ USER’S MANUAL For a more in-depth discussion of crystal specifications, ceramic resonators, and the selection of C1 and C2 see Applications Note AP-155, “Oscillators for Microcontrollers,” in the Embedded Applications handbook. 11.3.2 On-chip Oscillator (Ceramic Resonator) In cost-sensitive applications, you may choose a ceramic resonator instead of a crystal. Ceramic resonator applications may require slightly different capacitor values and circuit configuration.
MINIMUM HARDWARE SETUP For external clock drive requirements, see the device data sheet. Figure 11-4 shows the clock drive waveform. The external clock source must meet the minimum high and low times (TCHCX and TCLCX) and the maximum rise and fall times (TCLCH and TCHCL) to minimize the effect of external noise on the clock generator circuit. Long rise and fall times increase the chance that external noise will affect the clock circuitry and cause unreliable operation.
8XC251SA, SB, SP, SQ USER’S MANUAL The power off flag (POF) in the PCON register indicates whether a reset is a warm start or a cold start. A cold start reset (POF = 1) is a reset that occurs after power has been off or VCC has fallen below 3 V, so the contents of volatile memory are indeterminate. POF is set by hardware when VCC rises from less than 3V to its normal operating level. See section 12.2.2, “Power Off Flag.
MINIMUM HARDWARE SETUP While the RST pin is high ALE, PSEN#, and the port pins are weakly pulled high. The first ALE occurs 32TOSC after the reset signal goes low. For this reason, other devices can not be synchronized to the internal timings of the 8XC251Sx. NOTE Externally driving the ALE and/or PSEN# pins to 0 during the reset routine may cause the device to go into an indeterminate state.
8XC251SA, SB, SP, SQ USER’S MANUAL ≥ 64 TOSC RST XTAL 1 2 3 32 Internal Reset Routine PSEN# ALE First ALE A4103-01 Figure 11-5.
12 Special Operating Modes
CHAPTER 12 SPECIAL OPERATING MODES This chapter describes the power control (PCON) register and three special operating modes: idle, powerdown, and on-circuit emulation (ONCE). 12.1 GENERAL The idle and powerdown modes are power reduction modes for use in applications where power consumption is a concern. User instructions activate these modes by setting bits in the PCON register. Program execution halts, but resumes when the mode is exited by an interrupt.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: PCON S:87H 00XX 0000B 7 0 SMOD1 SMOD0 Bit Number Bit Mnemonic 7 SMOD1 — POF GF1 GF0 PD IDL Function Double Baud Rate Bit: When set, doubles the baud rate when timer 1 is used and mode 1, 2, or 3 is selected in the SCON register. See section 10.6, “Baud Rates.” 6 SMOD0 SCON.7 Select: When set, read/write accesses to SCON.7 are to the FE bit. When clear, read/write accesses to SCON.7 are to the SM0 bit.
SPECIAL OPERATING MODES Table 12-1.
8XC251SA, SB, SP, SQ USER’S MANUAL 12.3 IDLE MODE Idle mode is a power reduction mode that reduces power consumption to about 40% of normal. In this mode, program execution halts. Idle mode freezes the clocks to the CPU at known states while the peripherals continue to be clocked (Figure 12-2). The CPU status before entering idle mode is preserved; i.e., the program counter, program status word register, and register file retain their data for the duration of idle mode.
SPECIAL OPERATING MODES 12.3.2 Exiting Idle Mode There are two ways to exit idle mode: • Generate an enabled interrupt. Hardware clears the PCON register IDL bit which restores the clocks to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated idle mode.
8XC251SA, SB, SP, SQ USER’S MANUAL 12.4.1 Entering Powerdown Mode To enter powerdown mode, set the PCON register PD bit. The 8XC251Sx enters the power-down mode upon execution of the instruction that sets the PD bit. The instruction that sets the PD bit is the last instruction executed. 12.4.2 Exiting Powerdown Mode CAUTION If VCC was reduced during the powerdown mode, do not exit powerdown until VCC is restored to the normal operating level.
SPECIAL OPERATING MODES 12.5 ON-CIRCUIT EMULATION (ONCE) MODE The on-circuit emulation (ONCE) mode permits external testers to test and debug 8XC251Sxbased systems without removing the chip from the circuit board. A clamp-on emulator or test CPU is used in place of the 8XC251Sx which is electrically isolated from the system. 12.5.1 Entering ONCE Mode To enter the ONCE mode: 1. Assert RST to initiate a device reset. See section 11.4.
13 External Memory Interface
CHAPTER 13 EXTERNAL MEMORY INTERFACE 13.1 OVERVIEW The external memory interface comprises the external bus (ports 0 and 2, and when enabled also includes port 1.7:6) as well as the bus control signals (RD#, WR#, PSEN# and ALE).
8XC251SA, SB, SP, SQ USER’S MANUAL Table 13-1. External Memory Interface Signals Signal Name Type Alternate Function Description A17 O Address Line 17. P1.7/CEX4/WCLK A16 O Address Line 16. See RD#. P3.7/RD# A15:8† O Address Lines. Upper address for external bus (non-page mode). P2.7:0 AD7:0† I/O Address/Data Lines. Multiplexed lower address and data for the external bus (non-page mode). P0.7:0 ALE O Address Latch Enable.
EXTERNAL MEMORY INTERFACE 13.2 EXTERNAL BUS CYCLES The section describes the bus cycles the 8XC251Sx executes to fetch code, read data, and write data in external memory. Both page mode and nonpage mode are described and illustrated. For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. This section does not cover wait states (see section 13.
i_extmem.fm5 Page 4 Thursday, June 27, 1996 1:39 PM 8XC251SA, SB, SP, SQ USER’S MANUAL 13.2.2 Nonpage Mode Bus Cycles In nonpage mode, the external bus structure is the same as for MCS 51 microcontrollers. The upper address bits (A15:8) are on port 2, and the lower address bits (A7:0) are multiplexed with the data (D7:0) on port 0. External code read bus cycles execute in approximately two state times. See Table 13-2 and Figure 13-2.
EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 XTAL ALE WR# P0 A17/A16/P2 A7:0 D7:0 A17/A16/A15:8 A2808-03 Figure 13-4. External Data Write (Nonpage Mode) 13.2.3 Page Mode Bus Cycles Page mode increases performance by reducing the time for external code fetches. Under certain conditions the controller fetches an instruction from external memory in one state time instead of two (Table 13-2). Page mode does not affect internal code fetches.
8XC251SA, SB, SP, SQ USER’S MANUAL Figure 13-5 shows the two types of external bus cycles for code fetches in page mode. The pagemiss cycle is the same as a code fetch cycle in nonpage mode (except D7:0 is multiplexed with A15:8 on P2.). For the page-hit cycle, the upper eight address bits are the same as for the preceding cycle. Therefore, ALE is not asserted, and the values of A15:8 are retained in the address latches.
EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 XTAL ALE RD#/PSEN# A17/A16/P0 A17/A16/A7:0 P2 A15:8 D7:0 A2811-04 Figure 13-6. External Data Read (Page Mode) State 1 State 2 State 3 XTAL ALE WR# A17/A16/P0 P2 A17/A16/A7:0 A15:8 D7:0 A2810-03 Figure 13-7.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.3 WAIT STATES The 8XC251SA, SB, SP, SQ provides three types of wait state solutions to external memory problems: real-time, RD#/WR#/PSEN#, and ALE wait states. The 8XC251SA, SB, SP, SQ supports traditional real-time wait state operations for dynamic bus control. Real-time wait state operations are controlled by means of the WCON special function register. See section 13.5, “External Bus Cycles with Real-time Wait States.
EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 XTAL ALE RD#/PSEN# P0 A7:0 A17/A16/P2 D7:0 A17/A16/A15:8 A2812-04 Figure 13-8. External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) State 1 State 2 State 3 State 4 XTAL ALE WR# P0 A17/A16/P2 A7:0 D7:0 A17/A16/A15:8 A4174-02 Figure 13-9.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.4.2 Extending ALE Figure 13-10 shows the nonpage mode code fetch external bus cycle with ALE extended. The wait state extends the bus cycle from two states to three. For read and write external bus cycles, the extended ALE extends the bus cycle from three states to four. State 1 State 2 State 3 XTAL ALE RD#/PSEN# P0 A7:0 A17/A16/P2 A15:8 D7:0 A2813-04 Figure 13-10. External Code Fetch (Nonpage Mode, One ALE Wait State) 13.
EXTERNAL MEMORY INTERFACE Address: Reset State: WCON S:A7H XXXX XX00B 7 0 — Bit Number 7:2 — — — — Bit Mnemonic — — RTWCE RTWE Function Reserved: The values read from these bits are indeterminate. Write “0” to these bits. 1 RTWCE Real-time WAIT CLOCK enable. Write a ‘1’ to this bit to enable the WAIT CLOCK on port 1.7 (WCLK). The square wave output signal is one-half the oscillator frequency. 0 RTWE Real-time WAIT# enable.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.5.1 Real-time WAIT# Enable (RTWE) The real-time WAIT# input is enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal “system ready” to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input. Sampling of WAIT# is coincident with the activation of RD#/PSEN# or WR# signals driven low during a bus cycle.
EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 State 1 (next cycle) WCLK ALE RD#/PSEN# RD#/PSEN# stretched WAIT# P0 A0-A7 P2 D0-D7 stretched A8-A15 stretched A0-A7 A8-A15 A5007-01 Figure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State) State 1 State 2 State 3 State 4 WCLK ALE WR# WR# stretched WAIT# P0 P2 D0-D7 A0-A7 A8-A15 stretched stretched A5009-01 Figure 13-13.
8XC251SA, SB, SP, SQ USER’S MANUAL State 1 State 2 State 3 State 1 (next cycle) WCLK ALE RD#/PSEN# RD#/PSEN# stretched WAIT# P2 A8-A15 P0 D0-D7 stretched A0-A7 stretched A8-A15 A0-A7 A5008-01 Figure 13-14. External Data Read (Page Mode, RT Wait State) State 1 State 2 State 3 State 4 WCLK ALE WR# WR# stretched WAIT# P2 P0 A8-A15 D0-D7 A0-A7 stretched stretched A5010-01 Figure 13-15.
EXTERNAL MEMORY INTERFACE 13.6 CONFIGURATION BYTE BUS CYCLES If EA# = 0, devices obtain configuration information from a configuration array in external memory. This section describes the bus cycles executed by the reset routine to fetch user configuration bytes from external memory. Configuration bytes are discussed in Chapter 4, “Device Configuration.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.7 PORT 0 AND PORT 2 STATUS This section summarizes the status of the port 0 and port 2 pins when these ports are used as the external bus. A more comprehensive description of the ports and their use is given in Chapter 7, “Input/Output Ports.
EXTERNAL MEMORY INTERFACE 13.7.2 Port 0 and Port 2 Pin Status in Page Mode In a page-mode bus cycle, the data is multiplexed with the upper address byte on port 2. However, if the instruction uses an 8-bit address (e.g., MOVX @Ri), the contents of P2 are driven onto the pins when data is not on the pins. These logic levels can be used to select 256-bit pages in external memory. During bus idle, the port 0 and port 2 pins are held at high impedance.
i_extmem.fm5 Page 18 Thursday, June 27, 1996 1:40 PM 8XC251SA, SB, SP, SQ USER’S MANUAL 13.8 EXTERNAL MEMORY DESIGN EXAMPLES This section presents several external memory designs for 8XC251Sx systems. These examples illustrate the design flexibility provided by the configuration options, especially for the PSEN# and RD# signals. Many designs are possible. The examples employ the 8XC251SB but also apply to SA, SP, and SQ devices if the differences in on-chip memory are allowed for.
EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH FF: 0000H 128 Kbytes External Flash FE: 01: FFFFH 128 Kbytes –1056 Bytes External RAM 00: 0420H 00:0000H 1056 Bytes On-chip RAM A4220-02 Figure 13-18.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAM In this example, an 80C251SB operates in page mode with a 17-bit external address bus interfaced to 64 Kbytes of flash memory for code storage and 32 Kbytes of external RAM (Figure 13-19). The 80C251SB is configured so that PSEN# is asserted for all reads, and RD# functions as A16 (RD1:0 = 01). Figure 13-20 shows how the external flash and RAM are addressed in the internal address space.
EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH FF: 64 Kbytes External Flash 0000H FE: 01: 00: 0420H 00:0000H 7FFFH 32 Kbytes –1056 Bytes External RAM 1056 Bytes On-chip RAM A4168-03 Figure 13-20.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAM In this example, an 87C251SB/83C251SB operates in nonpage mode with a 17-bit external address bus interfaced to 128 Kbytes of external RAM (Figure 13-21). The 87C251SB/83C251SB is configured so that RD# functions as A16, and PSEN# is asserted for all reads. Figure 13-22 shows how the external RAM is addressed in the internal address space.
EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH FF: 0000H 3FFFH 16 Kbytes On-chip Code Memory FE: 128 Kbytes –1056 Bytes External RAM 01: FFFFH 00: 0420H 00:0000H 1056 Bytes On-chip RAM A4169-03 Figure 13-22.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAM In this example, an 87C251SB/83C251SB operates in nonpage mode with a 16-bit external address bus interfaced to 64 Kbytes of RAM (Figure 13-23). This configuration leaves P3.7/RD#/A16 available for general I/O (RD1:0 = 10). A maximum of 64 Kbytes of external memory can be used and all regions of internal memory map into the single 64-Kbyte region in external memory (see Figure 4-6 on page 4-11).
EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH FF: 0000H 3FFFH 16 Kbytes On-chip Code Memory FE: 01: FFFFH 00: External RAM 64 Kbytes – 1056 Bytes 0420H 00:0000H 1056 Bytes On-chip RAM A4224-02 Figure 13-24.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM In this example, an 80C251SB operates in nonpage mode with a 16-bit external address bus interfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM (Figure 13-25). The 80C251SB is configured so that RD# is asserted for addresses ≤ 7F:FFFFH and PSEN# is asserted for addresses ≥ 80:0000H. Figure 13-26 shows two ways to address the external memory in the internal memory space.
EXTERNAL MEMORY INTERFACE EPROM (64 Kbytes) 80C251SB EA# RAM (64 Kbytes) CE# CE# A15:8 A15:8 A15:8 P2 Code P0 WR# RD# PSEN# Data A7:0 A/D7:0 Latch A7:0 A7:0 D7:0 D7:0 OE# OE# WE# A4145-01 Figure 13-25.
8XC251SA, SB, SP, SQ USER’S MANUAL Address Space (256 Kbytes) Address Space (256 Kbytes) FFFFH FF: 64 Kbytes External EPROM FE: FE: 01: 01: FFFFH 0420H 64 Kbytes External EPROM FFFFH 64 Kbytes External RAM 0000H 0000H 00: FFFFH FF: External RAM 64 Kbytes – 1056 Bytes 1056 Bytes On-chip RAM 0000H 00: 0420H 00:0000H 1056 Bytes On-chip RAM 4175-03 Figure 13-26.
EXTERNAL MEMORY INTERFACE 13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAM In this example, an 80C251SB operates in page mode with a 16-bit external address bus interfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM (Figure 13-27). The 80C251SB is configured so that RD# is asserted for addresses ≤ 7F:FFFFH, and PSEN# is asserted for addresses ≥ 80:0000. This system is the same as Example 5 (Figure 13-25) except that it operates in page mode.
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External Flash In this example, an 80C251SB operates in page mode with a 17-bit external address bus interfaced to 128 Kbytes of flash memory (Figure 13-28). Port 2 carries both the upper address bits (A15:0) and the data (D7:0), while port 0 carries only the lower address bits (A7:0). The 80C251SB is configured for a single read signal (PSEN#).
14 Programming and Verifying Nonvolatile Memory
CHAPTER 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY This chapter provides instructions for programming and verifying on-chip nonvolatile memory on the 8XC251Sx. The programming instructions cover the entry of program code into on-chip code memory, configuration information into the on-chip configuration bytes, and other categories of information into on-chip memory outside the memory address space. The verify instructions permit reading these memory locations to verify their contents.
8XC251SA, SB, SP, SQ USER’S MANUAL In some microcontroller applications, it is desirable that user program code be secure from unauthorized access. The 8XC251Sx offers two types of protection for program code stored in the onchip array. • Program code in the on-chip code memory is encrypted when read out for verification if the encryption array is programmed. • A three-level lock bit system restricts external access to the on-chip code memory. 14.1.
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14.1.2 EPROM Devices On EPROM devices, the quartz window must be covered with an opaque label when the device is in operation. This is not so much to protect the EPROM array from inadvertent erasure, as to protect the RAM and other on-chip logic. Allowing light to impinge on the silicon die during device operation may cause a logical malfunction. 14.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 14-1. Programming and Verifying Modes Mode Address Port 1 (high) Port 3 (low) Notes RST PSEN# VPP PROG# Port 0 Port 2 Program Mode. On-chip Code Memory 8K 87C251SA,SP 16K 87C251SB,SQ High Low 5 V, 12.75 V 5 Pulses 68H data Verify Mode. On-chip Code Memory 8K 87/83C251SA,SP 16K 87/83C251SB,SQ High Program Mode. Configuration Bytes (UCONFIG0, UCONFIG1) 87C251Sx High Low 5 V, 12.75 V 5 Pulses 69H data FFF8H-FFFFH 1, 4 Verify Mode.
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY VCC 8XC251Sx A0 - A7 P3 A8 - A15 P1 VCC RST Address (16 Bits) P2 EA#/Vpp XTAL1 ALE/PROG# 4 MHz to 6 MHz Data (8 Bits) Programming Signals PSEN# XTAL2 VSS P0 Program/Verify Mode (8 Bits) A4122-02 Figure 14-1. Setup for Programming and Verifying Nonvolatile Memory 14.4 PROGRAMMING ALGORITHM The procedure for programming the 87C251Sx is as follows: 1. Set up the controller for operation in the appropriate mode according to Table 14-1. 2.
8XC251SA, SB, SP, SQ USER’S MANUAL Programming Cycle Verification Cycle Address (16-Bit) Address P1, P3 P2 Data In (8-Bit) Data Out PROG# 1 EA#/VPP 2 3 4 5 12.75V 5V P0 Mode (8-Bit) Mode A4129-01 Figure 14-2. Program/Verify Bus Cycles 14.5 VERIFY ALGORITHM Use this procedure to verify user program code, signature bytes, configuration bytes, and lock bits stored in nonvolatile memory on the 8XC251Sx.
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14.6.1 On-chip Code Memory On-chip code memory is located in the top region of the memory space starting at address FF:0000H. At reset, the 87C251Sx and 83C251Sx devices vector to this address. See Chapter 3, “Address Spaces,” for detailed information on the 8XC251Sx address space. To enter user program code and data in the on-chip code memory, perform the procedure described in 14.
8XC251SA, SB, SP, SQ USER’S MANUAL Table 14-2. Lock Bit Function Lock Bits Programmed Protection Type LB3 LB2 LB1 Level 1 U U U No program lock features are enabled. On-chip user code is encrypted when verified, if encryption array is programmed. Level 2 U U P External code is prevented from fetching code bytes from onchip code memory. Further programming of the on-chip OTPROM is disabled. Level 3 U P P Same as level 2, plus on-chip code memory verify is disabled.
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Table 14-3.
A Instruction Set Reference
i_opcode.fm5 Page 1 Thursday, June 27, 1996 1:41 PM APPENDIX A INSTRUCTION SET REFERENCE This appendix contains reference material for the instructions in the MCS® 251 architecture. It includes an opcode map, a summary of the instructions — with instruction lengths and execution times — and a detailed description of each instruction. It contains the following tables: • Tables A-1 through A-4 describe the notation used for the instruction operands.
8XC251SA, SB, SP, SQ USER’S MANUAL A.1 NOTATION FOR INSTRUCTION OPERANDS Table A-1.
INSTRUCTION SET REFERENCE Table A-2. Notation for Direct Addresses Direct Address. Description MCS® 251 Arch. MCS 51 Arch. ✔ dir8 An 8-bit direct address. This can be a memory address (00:0000H–00:00FFH) or an SFR address (S:00H - S:FFH). ✔ dir16 A 16-bit memory address (00:0000H–00:FFFFH) used in direct addressing. ✔ Table A-3. Notation for Immediate Addressing Immediate Data Description MCS® 251 Arch. MCS 51 Arch. ✔ #data An 8-bit constant that is immediately addressed in an instruction.
8XC251SA, SB, SP, SQ USER’S MANUAL A.2 OPCODE MAP AND SUPPORTING TABLES Table A-6. Instructions for MCS® 51 Microcontrollers Bin. 0 1 2 3 4 5 6-7 8-F Src.
INSTRUCTION SET REFERENCE Table A-7. New Instructions for the MCS® 251 Architecture Bin. A5x 8 A5 x9 A5x A A5 xB A5 xC A5x D A5 xE A5x F Src.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-8.
INSTRUCTION SET REFERENCE All of the bit instructions in the MCS 251 architecture (Table A-7) have opcode A9, which serves as an escape byte (similar to A5). The high nibble of byte 1 specifies the bit instruction, as given in Table A-10. Table A-10. Bit Instructions Instruction 1 Bit Instr (dir8) Byte 0(x) A 9 Byte 1 xxxx 0 bit Byte 2 Byte 3 dir8 addr rel addr Table A-11.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-12. PUSH/POP Instructions Instruction Byte 0(x) Byte 1 Byte 2 PUSH #data C A 0000 0010 #data PUSH #data16 C A 0000 0110 #data16 (high) PUSH Rm C A m 1000 PUSH WRj C A j/2 1001 PUSH DRk C A k/4 1011 MOV DRk,PC C A k/4 0001 POP Rm D A m 1000 POP WRj D A j/2 1001 POP DRk D A k/4 1011 Byte 3 #data16 (low) Table A-13.
INSTRUCTION SET REFERENCE Table A-14.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-15. INC/DEC Instruction Byte 0 Byte 1 1 INC Rm,#short 0 B m 00 ss 2 INC WRj,#short 0 B j/2 01 ss 3 INC DRk,#short 0 B k/4 11 ss 4 DEC Rm,#short 1 B m 00 ss 5 DEC WRj,#short 1 B j/2 01 ss 6 DEC DRk,#short 1 B k/4 11 ss Table A-16. Encoding for INC/DEC ss #short 00 1 01 2 10 4 Table A-17.
INSTRUCTION SET REFERENCE A.3 INSTRUCTION SET SUMMARY This section summarizes the MCS 251 architecture instruction set. Tables A-19 through A-27 list the instructions by category, providing for each instruction a short description, its length in bytes, and its execution time in states. NOTE The instruction execution times given in the tables are for code executing from on-chip code memory and for data that is read from and written to on-chip RAM.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-18.
INSTRUCTION SET REFERENCE Table A-18.
8XC251SA, SB, SP, SQ USER’S MANUAL A.3.2 Instruction Summaries Table A-19.
INSTRUCTION SET REFERENCE Table A-20.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-21.
INSTRUCTION SET REFERENCE Table A-23.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-23.
INSTRUCTION SET REFERENCE Table A-24.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-24.
INSTRUCTION SET REFERENCE Table A-24.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-25.
INSTRUCTION SET REFERENCE Table A-26.
8XC251SA, SB, SP, SQ USER’S MANUAL Table A-27.
INSTRUCTION SET REFERENCE Table A-27.
8XC251SA, SB, SP, SQ USER’S MANUAL A.4 INSTRUCTION DESCRIPTIONS This section describes each instruction in the MCS 251 architecture. See the note on page A-11 regarding execution times. Table A-28 defines the symbols (—, ✓, 1, 0,?) used to indicate the effect of the instruction on the flags in the PSW and PSW1 registers. For a conditional jump instruction, “!” indicates that a flag influences the decision to jump. Table A-28. Flag Symbols Symbol Description — The instruction does not modify the flag.
INSTRUCTION SET REFERENCE [Encoding] a10 a9 a8 1 0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ACALL (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ← (PC.7:0) (SP) ← (SP) + 1 ((SP)) ← (PC.15:8) (PC.10:0) ← page address a7 a6 a5 a4 a3 a2 a1 a0 ADD , Function: Add Description: Adds the source operand to the destination operand, which can be a register or the accumulator, leaving the result in the register or accumulator.
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ADD (A) ← (A) + #data ADD A,dir8 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
INSTRUCTION SET REFERENCE [Encoding] 0010 1100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ADD (Rmd) ← (Rmd) + (Rms) ssss SSSS tttt TTTT uuuu UUUU ADD WRjd,WRjs Binary Mode Source Mode Bytes: 3 2 States: 3 2 [Encoding] 0010 1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ADD (WRjd) ← (WRjd) + (WRjs) ADD DRkd,DRks Binary Mode Source Mode Bytes: 3 2 States: 5 4 [Encoding] 0010 1111 Hex Code in: Binary
8XC251SA, SB, SP, SQ USER’S MANUAL ADD WRj,#data16 Binary Mode Source Mode Bytes: 5 4 States: 4 3 [Encoding] 0010 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ADD (WRj) ← (WRj) + #data16 0100 #data hi #data low 1000 #data hi #data low ADD DRk,#0data16 Binary Mode Source Mode Bytes: 5 4 States: 6 5 [Encoding] 0010 1110 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ADD (DRk) ← (DRk) + #data16 A
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding Operation: ADD (WRj) ← (WRj) + (dir8) ADD Rm,dir16 Binary Mode Source Mode Bytes: 5 4 States: 3 2 [Encoding] 0010 1110 ssss Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ADD (Rm) ← (Rm) + (dir16) 0011 direct addr direct add 0111 direct addr direct addr ADD WRj,dir16 Binary Mode Source Mode Bytes: 5 4 States: 4 3 [Encoding] 0010 1110 tttt Hex Code in
8XC251SA, SB, SP, SQ USER’S MANUAL ADD Rm,@DRk Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] 0010 1110 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ADD (Rm) ← (Rm) + ((DRk)) 1011 ssss 0000 ADDC A, Function: Add with carry Description: Simultaneously adds the specified byte variable, the CY flag, and the accumulator contents, leaving the result in the accumulator.
INSTRUCTION SET REFERENCE [Encoding] Hex Code in: Operation: 0011 0100 immed. data Binary Mode = [Encoding] Source Mode = [Encoding] ADDC (A) ← (A) + (CY) + #data ADDC A,dir8 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
8XC251SA, SB, SP, SQ USER’S MANUAL AJMP addr11 Function: Absolute jump Description: Transfers program execution to the specified address, which is formed at run time by concatenating the upper five bits of the PC (after incrementing the PC twice), opcode bits 7– 5, and the second byte of the instruction. The destination must therefore be within the same 2-Kbyte “page” of program memory as the first byte of the instruction following AJMP.
INSTRUCTION SET REFERENCE Example: Register 1 contains 0C3H (11000011B) and register 0 contains 55H (01010101B). After executing the instruction ANL R1,R0 register 1 contains 41H (01000001B). When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM location or hardware register.
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ANL (A) ← (A) Λ #data ANL A,dir8 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
INSTRUCTION SET REFERENCE [Encoding] Hex Code in: Operation: 0101 1100 ssss SSSS tttt TTTT ssss 0000 Binary Mode = [A5][Encoding] Source Mode = [Encoding] ANL (Rmd) ← (Rmd) Λ (Rms) ANL WRjd,WRjs Binary Mode Source Mode Bytes: 3 2 States: 3 2 [Encoding] 0101 1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ANL (WRjd) ← (WRjd) Λ (WRjs) ANL Rm,#data Binary Mode Source Mode Bytes: 4 3 States: 3 2 [Encoding] 0101 1110 Hex Code in: Binary Mod
8XC251SA, SB, SP, SQ USER’S MANUAL ANL Rm,dir8 Binary Mode Source Mode Bytes: 4 3 States: 3† 2† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
INSTRUCTION SET REFERENCE [Encoding] 0101 1110 tttt 0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ANL (WRj) ← (WRj) Λ (dir16) direct direct ANL Rm,@WRj Binary Mode Source Mode Bytes: 4 3 States: 3 2 [Encoding] 0101 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ANL (Rm) ← (Rm) Λ ((WRj)) 1001 ssss 0000 1011 ssss 0000 ANL Rm,@DRk Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] 0101
8XC251SA, SB, SP, SQ USER’S MANUAL Flags: Example: CY AC OV N Z ✓ — — — — Set the CY flag if, and only if, P1.0 = 1, ACC. 7 = 1, and OV = 0: MOV CY,P1.0 ;Load carry with input pin state ANL CY,ACC.7 ;AND carry with accumulator bit 7 ANL CY,/OV ;AND with inverse of overflow flag ANL CY,bit51 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
INSTRUCTION SET REFERENCE Operation: ANL (CY) ← (CY) Λ (bit) ANL CY,/bit Binary Mode Source Mode Bytes: 4 3 States: 3† 2† †If this instruction addresses a port (Px, x = 0–3), add 1 state. [Encoding] 1010 1001 1111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ANL (CY) ← (CY) Λ Ø (bit) 0 yyy dir addr CJNE ,,rel Function: Compare and jump if not equal.
8XC251SA, SB, SP, SQ USER’S MANUAL Variations CJNE A,#data,rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: 3 3 3 3 States: 2 5 2 5 [Encoding] 1011 0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (PC) ← (PC) + 3 IF (A) ≠ #data THEN (PC) ← (PC) + relative offset IF (A) < #data THEN (CY) ← 1 ELSE (CY) ← 0 immed. data rel.
INSTRUCTION SET REFERENCE [Encoding] 1011 011i Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: (PC) ← (PC) + 3 IF ((Ri)) ≠ #data THEN (PC) ← (PC) + relative offset IF ((Ri)) < #data THEN (CY) ← 1 ELSE (CY) ← 0 immed. data rel.
8XC251SA, SB, SP, SQ USER’S MANUAL Binary Mode Source Mode Bytes: 1 1 States: 1 1 [Encoding] 1110 0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: CLR (A) ← 0 CLR bit Function: Clear bit Description: Clears the specified bit. CLR can operate on the CY flag or any directly addressable bit. Flags: Only for instructions with CY as the operand. Example: CY AC OV N Z ✓ — — — — Port 1 contains 5DH (01011101B). After executing the instruction CLR P1.
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: CLR (CY) ← 0 CLR bit Binary Mode Source Mode Bytes: 4 4 States: 4† 3† †If this instruction addresses a port (Px, x = 0–3), add 2 states. [Encoding] 1010 1001 1100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CLR (bit) ← 0 0 yyy dir addr CMP , Function: Compare Description: Subtracts the source operand from the destination operand.
8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 1011 1100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CMP (Rmd) – (Rms) ssss SSSS tttt TTTT uuuu UUUU ssss 0000 CMP WRjd,WRjs Binary Mode Source Mode Bytes: 3 2 States: 3 2 [Encoding] 1011 1110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CMP (WRjd) – (WRjs) CMP DRkd,DRks Binary Mode Source Mode Bytes: 3 2 States: 5 4 [Encoding] 1011 1111 Hex Code in: Bi
INSTRUCTION SET REFERENCE CMP WRj,#data16 Binary Mode Source Mode Bytes: 5 4 States: 4 3 [Encoding] 1011 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CMP (WRj) – #data16 0100 #data hi #data low 1000 #data hi #data low 1100 #data hi #data hi CMP DRk,#0data16 Binary Mode Source Mode Bytes: 5 4 States: 6 5 [Encoding] 1011 1110 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CMP (DRk) – #0data16
8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 1011 1110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CMP (Rm) – (dir8) ssss 0001 dir addr tttt 0101 dir addr CMP WRj,dir8 Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] Hex Code in: Operation: 1011 1 1 10 Binary Mode = [A5][Encoding] Source Mode = [Encoding] CMP (WRj) – (dir8) CMP Rm,dir16 Binary Mode Source Mode Bytes: 5 4 States: 3 2 [Encoding] 1011 1110 ssss Hex Code in: Binar
INSTRUCTION SET REFERENCE CMP Rm,@WRj Binary Mode Source Mode Bytes: 4 3 States: 3 2 [Encoding] 1011 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CMP (Rm) – ((WRj)) 1001 ssss 0000 1011 ssss 0000 CMP Rm,@DRk Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] 1011 1110 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: CMP (Rm) – ((DRk)) CPL A Function: Complement accumulator Description:
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: CPL (A) ← Ø(A) CPL bit Function: Description: Complement bit Complements (Ø) the specified bit variable. A clear bit is set, and a set bit is cleared. CPL can operate on the CY or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin.
INSTRUCTION SET REFERENCE Operation: CPL (CY) ← Ø(CY) CPL bit Binary Mode Source Mode Bytes: 4 3 States: 4† 3† †If this instruction addresses a port (Px, x = 0–3), add 2 states.
8XC251SA, SB, SP, SQ USER’S MANUAL Example: The accumulator contains 56H (01010110B), which represents the packed BCD digits of the decimal number 56. Register 3 contains 67H (01100111B), which represents the packed BCD digits of the decimal number 67. The CY flag is set. After executing the instruction sequence ADDC A,R3 DA A the accumulator contains 0BEH (10111110) and the CY and AC flags are clear.
INSTRUCTION SET REFERENCE Example: Register 0 contains 7FH (01111111B). On-chip RAM locations 7EH and 7FH contain 00H and 40H, respectively. After executing the instruction sequence DEC @R0 DEC R0 DEC @R0 register 0 contains 7EH and on-chip RAM locations 7EH and 7FH are set to 0FFH and 3FH, respectively.
8XC251SA, SB, SP, SQ USER’S MANUAL DEC Rn Binary Mode Source Mode Bytes: 1 2 States: 1 2 [Encoding] 0001 1rrr Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: DEC (Rn) ← (Rn) – 1 DEC , Function: Decrement Description: Decrements the specified variable at the destination operand by 1, 2, or 4. An original value of 00H underflows to 0FFH. Flags: Example: CY AC OV N Z — — — ✓ ✓ Register 0 contains 7FH (01111111B).
INSTRUCTION SET REFERENCE [Encoding] 0001 1011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: DEC (WRj) ← (WRj) – #short tttt 01 vv uuuu 11 vv DEC DRk,#short Binary Mode Source Mode Bytes: 3 2 States: 5 4 [Encoding] 0001 1011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: DEC (DRk) ← (DRk) – #short DIV , Function: Divide Description: Divides the unsigned integer in the register by the unsigned integer op
8XC251SA, SB, SP, SQ USER’S MANUAL Variations DIV Rmd Rms Binary Mode Source Mode Bytes: 3 2 States: 11 10 [Encoding] 1000 1100 ssss SSSS Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: DIV (8-bit operands) (Rmd) ← remainder (Rmd) / (Rms) if md = 0,2,4,..,14 (Rmd+1) ← quotient (Rmd) / (Rms) (Rmd–1) ← remainder (Rmd) / (Rms) if md = 1,3,5,..
INSTRUCTION SET REFERENCE Exception: if register B contains 00H, the values returned in the accumulator and register B are undefined; the CY flag is cleared and the OV flag is set. Flags: CY AC OV N Z 0 — ✓ ✓ ✓ CY AC OV N Z 0 — 1 ? ? For division by zero: Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Example: The accumulator contains 251 (0FBH or 11111011B) and register B contains 18 (12H or 00010010B).
8XC251SA, SB, SP, SQ USER’S MANUAL Example: The on-chip RAM locations 40H, 50H, and 60H contain 01H, 70H, and 15H, respectively. After executing the following instruction sequence DJNZ 40H,LABEL1 DJNZ 50H,LABEL2 DJNZ 60H,LABEL on-chip RAM locations 40H, 50H, and 60H contain 00H, 6FH, and 14H, respectively, and program execution continues at label LABEL2. (The first jump was not taken because the result was zero.
INSTRUCTION SET REFERENCE Operation: DJNZ (PC) ← (PC) + 2 (Rn) ← (Rn) – 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) ← (PC) + rel ECALL Function: Extended call Description: Calls a subroutine located at the specified address. The instruction adds four to the program counter to generate the address of the next instruction and then pushes the 24-bit result onto the stack (high byte first), incrementing the stack pointer by three.
8XC251SA, SB, SP, SQ USER’S MANUAL ECALL @DRk Binary Mode Source Mode Bytes: 3 2 States: 12 11 [Encoding] 1001 1001 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ECALL (PC) ← (PC) + 4 (SP) ← (SP) + 1 ((SP)) ← (PC.23:16) (SP) ← (SP) + 1 ((SP)) ← (PC.15:8) (SP) ← (SP) + 1 ((SP)) ← (PC.
INSTRUCTION SET REFERENCE EJMP @DRk Binary Mode Source Mode Bytes: 3 2 States: 7 6 [Encoding] 1000 1001 uuuu Hex Code in: Binary Mode = [A5] [Encoding] Source Mode = [Encoding] Operation: EJMP (PC) ← ((DRk)) ERET Function: Extended return Description: Pops byte 2, byte 1, and byte 0 of the 3-byte PC successively from the stack and decrements the stack pointer by 3. Program execution continues at the resulting address, which normally is the instruction immediately following ECALL.
8XC251SA, SB, SP, SQ USER’S MANUAL Flags: Example: CY AC OV N Z — — — ✓ ✓ Register 0 contains 7EH (011111110B) and on-chip RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. After executing the instruction sequence INC @R0 INC R0 INC @R0 register 0 contains 7FH and on-chip RAM locations 7EH and 7FH contain 00H and 41H, respectively.
INSTRUCTION SET REFERENCE Operation: INC ((Ri) ← ((Ri)) + 1 INC Rn Binary Mode Source Mode Bytes: 1 2 States: 1 2 [Encoding] 0000 1rrr Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: INC (Rn) ← (Rn) + 1 INC , Function: Increment Description: Increments the specified variable by 1, 2, or 4. An original value of 0FFH overflows to 00H. Flags: Example: CY AC OV N Z — — — ✓ ✓ Register 0 contains 7EH (011111110B).
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: INC (WRj) ← (WRj) + #short INC DRk,#short Binary Mode Source Mode Bytes: 3 2 States: 4 3 [Encoding] 0000 1011 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: INC (DRk) ← (DRk) + #shortdata pointer 11 vv INC DPTR Function: Increment data pointer Description: Increments the 16-bit data pointer by one.
INSTRUCTION SET REFERENCE JB bit51,rel JB bit,rel Function: Jump if bit set Description: If the specified bit is a one, jump to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified.
8XC251SA, SB, SP, SQ USER’S MANUAL Operation: JB (PC) ← (PC) + 3 IF (bit) = 1 THEN (PC) ← (PC) + rel JBC bit51,rel JBC bit,rel Function: Description: Jump if bit is set and clear bit If the specified bit is one, branch to the specified address; otherwise proceed with the next instruction. The bit is not cleared if it is already a zero.
INSTRUCTION SET REFERENCE JBC bit,rel Binary Mode Source Mode Not Taken Taken Not Taken Bytes: 5 5 4 Taken 4 States: 4 7 3 6 [Encoding] 1010 1001 0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: JBC (PC) ← (PC) + 3 IF (bit51) = 1 THEN (bit51) ← 0 (PC) ← (PC) + rel 0 yyy direct addr rel. addr JC rel Function: Jump if carry is set Description: If the CY flag is set, branch to the address specified; otherwise proceed with the next instruction.
8XC251SA, SB, SP, SQ USER’S MANUAL Operation: JC (PC) ← (PC) + 2 IF (CY) = 1 THEN (PC) ← (PC) + rel JE rel Function: Jump if equal Description: If the Z flag is set, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice. Flags: Example: CY AC OV N Z — — — — ! The Z flag is set.
INSTRUCTION SET REFERENCE Example: The instruction JG LABEL1 causes program execution to continue at label LABEL1 if the Z flag and the CY flag are both clear. Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: 3 3 2 2 States: 2 5 1 4 [Encoding] 0011 1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: JG (PC) ← (PC) + 2 IF (Z) = 0 AND (CY) = 0 THEN (PC) ← (PC) + rel rel.
8XC251SA, SB, SP, SQ USER’S MANUAL Operation: JLE (PC) ← (PC) + 2 IF (Z) = 1 OR (CY) = 1 THEN (PC) ← (PC) + rel JMP @A+DPTR Function: Jump indirect Description: Add the 8-bit unsigned contents of the accumulator with the 16-bit data pointer and load the resulting sum into the lower 16 bits of the program counter. This is the address for subsequent instruction fetches. The contents of the accumulator and the data pointer are not affected.
INSTRUCTION SET REFERENCE Flags: Example: CY AC OV N Z — — — — — Input port 1 contains 11001010B and the accumulator contains 56H (01010110B). After executing the instruction sequence JNB P1.3,LABEL1 JNB ACC.3,LABEL2 program execution continues at label LABEL2.
8XC251SA, SB, SP, SQ USER’S MANUAL JNC rel Function: Jump if carry not set Description: If the CY flag is clear, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The CY flag is not modified. Flags: Example: CY AC OV N Z ! — — — — The CY flag is set.
INSTRUCTION SET REFERENCE Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: 3 3 2 2 States: 2 5 1 4 [Encoding] 0111 1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: JNE (PC) ← (PC) + 2 IF (Z) = 0 THEN (PC) ← (PC) + rel rel. addr JNZ rel Function: Jump if accumulator not zero Description: If any bit of the accumulator is set, branch to the specified address; otherwise proceed with the next instruction.
8XC251SA, SB, SP, SQ USER’S MANUAL JSG rel Function: Jump if greater than (signed) Description: If the Z flag is clear AND the N flag and the OV flag have the same value, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
INSTRUCTION SET REFERENCE Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: 3 3 2 2 States: 2 5 1 4 [Encoding] 0101 1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: JSGE (PC) ← (PC) + 2 IF [(N) = (OV)] THEN (PC) ← (PC) + rel rel. addr JSL rel Function: Jump if less than (signed) Description: If the N flag and the OV flag have different values, branch to the address specified; otherwise proceed with the next instruction.
8XC251SA, SB, SP, SQ USER’S MANUAL JSLE rel Function: Jump if less than or equal (signed) Description: If the Z flag is set OR if the the N flag and the OV flag have different values, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
INSTRUCTION SET REFERENCE Example: The accumulator contains 01H. After executing the instruction sequence JZ LABEL1 DEC A JZ LABEL2 the accumulator contains 00H and program execution continues at label LABEL2. Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: 2 2 2 2 States: 2 5 2 5 [Encoding] 0110 0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: JZ (PC) ← (PC) + 2 IF (A) = 0 THEN (PC) ← (PC) + rel rel.
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1 ((SP)) ← (PC.7:0) (SP) ← (SP) + 1 ((SP)) ← (PC.15:8) (PC) ← (addr.15:0) LCALL @WRj Binary Mode Source Mode Bytes: 3 2 States: 9 8 [Encoding] 1001 1001 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1 ((SP)) ← (PC.7:0) (SP) ← (SP) + 1 ((SP)) ← (PC.
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: LJMP (PC) ← (addr.15:0) LJMP @WRj Binary Mode Source Mode Bytes: 3 2 States: 6 5 [Encoding] 1000 1001 tttt Hex Code in: Binary Mode = [A5] [Encoding] Source Mode = [Encoding] Operation: LJMP (PC) ← ((WRj)) 0100 MOV , Function: Move byte variable Description: Copies the byte variable specified by the second operand into the location specified by the first operand.
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: MOV (A) ← #data MOV dir8,#data Binary Mode Source Mode Bytes: 3 3 States: 3† 3† †If this instruction addresses a port (Px, x = 0–3), add 1 state. [Encoding] 0111 0101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: MOV (dir8) ← #data direct addr MOV @Ri,#data Binary Mode Source Mode Bytes: 2 3 States: 3 4 [Encoding] 0111 011i immed.
INSTRUCTION SET REFERENCE [Encoding] 1000 0101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: MOV (dir8) ← (dir8) direct addr direct addr MOV dir8,@Ri Binary Mode Source Mode Bytes: 2 3 States: 3 4 [Encoding] 1000 011i direct addr Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: MOV (dir8) ← ((Ri)) MOV dir8,Rn Binary Mode Source Mode Bytes: 2 3 States: 2† 3† †If this instruction addresses a port (Px, x = 0–3), add 1 st
8XC251SA, SB, SP, SQ USER’S MANUAL MOV Rn,dir8 Binary Mode Source Mode Bytes: 2 3 States: 1† 2† †If this instruction addresses a port (Px, x = 0–3), add 1 state. [Encoding] 1010 1rrr direct addr Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: MOV (Rn) ← (dir8) MOV A,dir8 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
INSTRUCTION SET REFERENCE Operation: MOV (A) ← (Rn) MOV dir8,A Binary Mode Source Mode Bytes: 2 2 States: 2† 2† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (Rmd) ← (Rms) MOV WRjd,WRjs Binary Mode Source Mode Bytes: 3 2 States: 2 1 [Encoding] 0111 1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRjd) ← (WRjs) tttt TTTT uuuu UUUU ssss 0000 MOV DRkd,DRks Binary Mode Source Mode Bytes: 3 2 States: 3 2 [Encoding] 0111 1111 Hex Code in: Binary Mode = [A5][Encoding] Source Mo
INSTRUCTION SET REFERENCE [Encoding] 0111 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRj) ← #data16 0100 #data hi #data low 1000 #data hi #data low 1100 #data hi #data low MOV DRk,#0data16 Binary Mode Source Mode Bytes: 5 4 States: 5 4 [Encoding] 0111 1110 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (DRk) ← #0data16 MOV DRk,#1data16 Binary Mode Source Mode Bytes: 5 4 States: 5 4
8XC251SA, SB, SP, SQ USER’S MANUAL Operation: MOV (Rm) ← (dir8) MOV WRj,dir8 Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] 0111 1110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRj) ← (dir8) tttt 0101 direct addr uuuu 1101 direct addr MOV DRk,dir8 Binary Mode Source Mode Bytes: 4 3 States: 6 5 [Encoding] 0111 1110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (DRk) ← (dir8) MOV Rm,di
INSTRUCTION SET REFERENCE [Encoding] 0111 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRj) ← (dir16) 0111 direct addr direct addr 1111 direct addr direct addr MOV DRk,dir16 Binary Mode Source Mode Bytes: 5 4 States: 6 5 [Encoding] 0111 1110 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (DRk) ← (dir16) MOV Rm,@WRj Binary Mode Source Mode Bytes: 4 3 States: 2 2 [Encoding] 0111 1110
8XC251SA, SB, SP, SQ USER’S MANUAL MOV WRjd,@WRjs Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] 0000 1011 TTTT Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRjd) ← ((WRjs)) 1000 tttt 0000 1010 tttt 0000 MOV WRj,@DRk Binary Mode Source Mode Bytes: 4 3 States: 5 4 [Encoding] 0000 1011 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRj) ← ((DRk)) MOV dir8,Rm Binary Mode Source Mode
INSTRUCTION SET REFERENCE [Encoding] 0111 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (dir8) ← (WRj) tttt 0101 direct addr uuuu 1101 direct addr MOV dir8,DRk Binary Mode Source Mode Bytes: 4 3 States: 7 6 [Encoding] 0111 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (dir8) ← (DRk) MOV dir16,Rm Binary Mode Source Mode Bytes: 5 4 States: 4 3 [Encoding] 0111 1010 ssss Hex Code in: Binary
8XC251SA, SB, SP, SQ USER’S MANUAL MOV dir16,DRk Binary Mode Source Mode Bytes: 5 4 States: 7 6 [Encoding] 0111 1010 uuuu 1111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (dir16) ← (DRk) direct addr direct addr MOV @WRj,Rm Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] 0111 1010 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV ((WRj)) ← (Rm) 1001 ssss 0000 1011 ssss 0000 1000 TTTT
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV ((WRjd)) ← (WRjs) MOV @DRk,WRj Binary Mode Source Mode Bytes: 4 3 States: 6 5 [Encoding] 0001 1011 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV ((DRk)) ← (WRj) 1010 tttt 0000 MOV Rm,@WRj + dis16 Binary Mode Source Mode Bytes: 5 4 States: 6 5 [Encoding] 0000 1001 ssss Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [En
8XC251SA, SB, SP, SQ USER’S MANUAL MOV Rm,@DRk + dis24 Binary Mode Source Mode Bytes: 5 4 States: 7 6 [Encoding] 0010 1001 ssss Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (Rm) ← ((DRk)) + (dis) uuuu dis hi dis low uuuu dis hi dis low ssss dis hi dis low MOV WRj,@DRk + dis24 Binary Mode Source Mode Bytes: 5 4 States: 8 7 [Encoding] 0110 1001 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRj
INSTRUCTION SET REFERENCE [Encoding] 0101 1001 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV ((WRj)) + (dis) ← (WRj) TTTT dis hi dis low ssss dis hi dis low tttt dis hi dis low MOV @DRk + dis24,Rm Binary Mode Source Mode Bytes: 5 4 States: 7 6 [Encoding] 0011 1001 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV ((DRk)) + (dis) ← (Rm) MOV @DRk + dis24,WRj Binary Mode Source Mode Bytes: 5 4 Sta
8XC251SA, SB, SP, SQ USER’S MANUAL Example: The CY flag is set, input Port 3 contains 11000101B, and output Port 1 contains 35H (00110101B). After executing the instruction sequence MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY the CY flag is clear and Port 1 contains 39H (00111001B). Variations MOV bit51,CY Binary Mode Source Mode Bytes: 2 2 States: 2† 2† †If this instruction addresses a port (Px, x = 0–3), add 2 states.
INSTRUCTION SET REFERENCE Operation: MOV (bit) ← (CY) MOV CY,bit Binary Mode Source Mode Bytes: 4 3 States: 3† 2† †If this instruction addresses a port (Px, x = 0–3), add 1 state. [Encoding] 1010 1001 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (CY) ← (bit) 0 yyy direct addr MOV DPTR,#data16 Function: Load data pointer with a 16-bit constant Description: Loads the 16-bit data pointer (DPTR) with the specified 16-bit constant.
8XC251SA, SB, SP, SQ USER’S MANUAL MOVC A,@A+ Function: Move code byte Description: Loads the accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit accumulator contents and the contents of a 16-bit base register, which may be the 16 LSBs of the data pointer or PC.
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: MOVC (A) ← ((A) + (DPTR)) MOVH DRk,#data16 Function: Move immediate 16-bit data to the high word of a dword (double-word) register Description: Moves 16-bit immediate data to the high word of a dword (32-bit) register. The low word of the dword register is unchanged. Flags: Example: CY AC OV N Z — — — — — The dword register DRk contains 5566 7788H.
8XC251SA, SB, SP, SQ USER’S MANUAL Example: Eight-bit register Rm contains 055H (01010101B) and the 16-bit register WRj contains 0FFFFH (11111111 11111111B). The instruction MOVS WRj,Rm moves the contents of register Rm (01010101B) to register WRj (i.e., WRj contains 00000000 01010101B). Variations MOVS WRj,Rm Binary Mode Source Mode Bytes: 3 2 States: 2 1 [Encoding] Hex Code in: Operation: 0001 1010 tttt ssss Binary Mode = [A5][Encoding] Source Mode = [Encoding] MOVS (WRj).7–0 ← (Rm).
INSTRUCTION SET REFERENCE Example: The MCS 251 controller is operating in nonpage mode. An external 256-byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/I/O/Timer) is connected to port 0. Port 3 provides control lines for the external RAM. ports 1 and 2 are used for normal I/O. R0 and R1 contain 12H and 34H. Location 34H of the external RAM contains 56H. After executing the instruction sequence MOVX A,@R1 MOVX @R0,A the accumulator and external RAM location 12H contain 56H.
8XC251SA, SB, SP, SQ USER’S MANUAL MOVX @Ri,A Binary Mode Source Mode Bytes: 1 1 States: 4 4 [Encoding] 1111 001i Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: MOVX ((Ri)) ← (A) MOVZ WRj,Rm Function: Move 8-bit register to 16-bit register with zero extension Description: Moves the contents of an 8-bit register to the low byte of a 16-bit register. The upper byte of the 16-bit register is filled with zeros.
INSTRUCTION SET REFERENCE MUL , Function: Multiply Description: Multiplies the unsigned integer in the source register with the unsigned integer in the destination register. Only register addressing is allowed. For 8-bit operands, the result is 16 bits. The most significant byte of the result is stored in the low byte of the word where the destination register resides. The least significant byte is stored in the following byte register.
8XC251SA, SB, SP, SQ USER’S MANUAL MUL WRjd,WRjs Binary Mode Source Mode Bytes: 3 2 States: 12 11 [Encoding] 1010 1101 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MUL (16-bit operands) if jd = 0, 4, 8, .., 28 WRjd ← high word of the WRjd X WRjs WRjd+2 ← low word of the WRjd X WRjs if jd = 2, 6, 10, ..
INSTRUCTION SET REFERENCE NOP Function: No operation Description: Execution continues at the following instruction. Affects the PC register only. Flags: Example: CY AC OV N Z — — — — — You want to produce a low-going output pulse on bit 7 of Port 2 that lasts exactly 11 states. A simple CLR-SETB sequence generates an eight-state pulse. (Each instruction requires four states to write to a port SFR.
8XC251SA, SB, SP, SQ USER’S MANUAL Example: The accumulator contains 0C3H (11000011B) and R0 contains 55H (01010101B). After executing the instruction ORL A,R0 the accumulator contains 0D7H (11010111B). When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be a constant data value in the instruction or a variable computed in the accumulator at run time.
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ORL (A) ← (A) V #data ORL A,dir8 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ORL (Rmd) ← (Rmd) V (Rms) ORL WRjd,WRjs Binary Mode Source Mode Bytes: 3 2 States: 3 2 [Encoding] 0100 1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ORL (WRjd)←(WRjd) V (WRjs) tttt TTTT ssss 0000 ORL Rm,#data Binary Mode Source Mode Bytes: 4 3 States: 3 2 [Encoding] 0100 1110 Hex Code in Binary Mode = [A5][Encoding] Source M
INSTRUCTION SET REFERENCE ORL Rm,dir8 Binary Mode Source Mode Bytes: 4 3 States: 3† 2† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 0100 1110 tttt 0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ORL (WRj) ← (WRj) V (dir16) direct addr direct addr ORL Rm,@WRj Binary Mode Source Mode Bytes: 4 3 States: 3 2 [Encoding] 0100 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ORL (Rm) ← (Rm) V ((WRj)) 1001 ssss 0000 1011 ssss 0000 ORL Rm,@DRk Binary Mode Source Mode Bytes: 4 3 States: 4 3
INSTRUCTION SET REFERENCE Example: Set the CY flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0: MOV CY,P1.0 ;LOAD CARRY WITH INPUT PIN P10 ORL CY,ACC.7 ;OR CARRY WITH THE ACC. BIT 7 ORL CY,/OV ;OR CARRY WITH THE INVERSE OF OV. Variations ORL CY,bit51 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
8XC251SA, SB, SP, SQ USER’S MANUAL ORL CY,/bit Binary Mode Source Mode Bytes: 4 3 States: 3† 2† †If this instruction addresses a port (Px, x = 0–3), add 1 state. [Encoding] 1010 1001 1110 0 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ORL (CY) ← (CY) V ¬ (bit) yyy direct addr POP Function: Pop from stack Description: Reads the contents of the on-chip RAM location addressed by the stack pointer, then decrements the stack pointer by one.
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: POP (dir8) ← ((SP)) (SP) ← (SP) – 1 POP Rm Binary Mode Source Mode Bytes: 3 2 States: 3 2 [Encoding] 1101 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: POP (Rm) ← ((SP)) (SP) ← (SP) – 1 ssss 1000 tttt 1001 uuuu 1011 POP WRj Binary Mode Source Mode Bytes: 3 2 States: 5 4 [Encoding] 1101 1010 Hex Code in: Binary Mode = [A5][Encoding] Sou
8XC251SA, SB, SP, SQ USER’S MANUAL PUSH Function: Push onto stack Description: Increments the stack pointer by one. The contents of the specified variable are then copied into the on-chip RAM location addressed by the stack pointer. Flags: Example: CY AC OV N Z — — — — — On entering an interrupt routine, the stack pointer contains 09H and the data pointer contains 0123H.
INSTRUCTION SET REFERENCE PUSH #data16 Binary Mode Source Mode Bytes: 5 4 States: 6 5 [Encoding] 1100 1010 0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: PUSH (SP) ← (SP) + 2 ((SP)) ← MSB of #data16 ((SP)) ← LSB of #data16 0110 #data hi #data lo PUSH Rm Binary Mode Source Mode Bytes: 3 2 States: 4 3 [Encoding] 1100 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: PUSH (SP) ← (SP) + 1 ((SP)) ← (Rm) ssss 1
8XC251SA, SB, SP, SQ USER’S MANUAL PUSH DRk Binary Mode Source Mode Bytes: 3 2 States: 9 8 [Encoding] 1100 1010 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: PUSH (SP) ← (SP) + 1 ((SP)) ← (DRk) (SP) ← (SP) + 3 1011 RET Function: Return from subroutine Description: Pops the high and low bytes of the PC successively from the stack, decrementing the stack pointer by two.
INSTRUCTION SET REFERENCE RETI Function: Return from interrupt Description: This instruction pops two or four bytes from the stack, depending on the INTR bit in the CONFIG1 register. If INTR = 0, RETI pops the high and low bytes of the PC successively from the stack and uses them as the 16-bit return address in region FF:. The stack pointer is decremented by two. No other registers are affected, and neither PSW nor PSW1 is automatically restored to its pre-interrupt status.
8XC251SA, SB, SP, SQ USER’S MANUAL Operation for INTR = 1: RETI (PC).15:8 ← ((SP)) (SP) ← (SP) – 1 PC).7:0 ← ((SP)) (SP) ← (SP) – 1 (PC).23:16 ← ((SP)) (SP) ← (SP) – 1 PSW1 ← ((SP)) (SP) ← (SP) – 1 RL A Function: Rotate accumulator left Description: Rotates the eight bits in the accumulator one bit to the left. Bit 7 is rotated into the bit 0 position. Flags: Example: CY AC OV N Z — — — ✓ ✓ The accumulator contains 0C5H (11000101B).
INSTRUCTION SET REFERENCE Example: The accumulator contains 0C5H (11000101B) and the CY flag is clear. After executing the instruction RLC A the accumulator contains 8AH (10001010B) and the CY flag is set. Binary Mode Source Mode Bytes: 1 1 States: 1 1 [Encoding] 0011 0011 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: RLC (A).a+1 ← (A).a (A).0 ← (CY) (CY) ← (A) .
8XC251SA, SB, SP, SQ USER’S MANUAL RRC A Function: Rotate accumulator right through carry flag Description: Rotates the eight bits in the accumulator and the CY flag one bit to the right. Bit 0 moves into the CY flag position; the original value of the CY flag moves into the bit 7 position. Flags: Example: CY AC OV N Z ✓ — — ✓ ✓ The accumulator contains 0C5H (11000101B) and the CY flag is clear.
INSTRUCTION SET REFERENCE SETB bit51 Binary Mode Source Mode Bytes: 2 2 States: 2† 2† †If this instruction addresses a port (Px, x = 0–3), add 2 states.
8XC251SA, SB, SP, SQ USER’S MANUAL Flags: Example: CY AC OV N Z — — — — — The label "RELADR" is assigned to an instruction at program memory location 0123H. The instruction SJMP RELADR assembles into location 0100H. After executing the instruction, the PC contains 0123H. (Note: In the above example, the instruction following SJMP is located at 102H. Therefore, the displacement byte of the instruction is the relative offset (0123H–0102H) = 21H.
INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SLL (Rm).a+1 ← (Rm).a (Rm).0 ← 0 CY ← (Rm).7 SLL WRj Binary Mode Source Mode Bytes: 3 2 States: 2 1 [Encoding] 0011 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SLL WRj).b+1 ← (WRj).b (WRj).0 ← 0 CY ← (WRj).
8XC251SA, SB, SP, SQ USER’S MANUAL SRA WRj Binary Mode Source Mode Bytes: 3 2 States: 2 1 [Encoding] 0000 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SRA (WRj).15 ← (WRj).15 (WRj).b ← (WRj).b+1 CY ← (WRj).0 0100 SRL Function: Shift logical right by 1 bit Description: SRL shifts the specified variable to the right by 1 bit, replacing the MSB with a zero. The bit shifted out (LSB) is stored in the CY bit.
INSTRUCTION SET REFERENCE SRL WRj Binary Mode Source Mode Bytes: 3 2 States: 2 1 [Encoding] 0001 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SRL (WRj).15 ← 0 (WRj).b ← (WRj).b+1 CY← (WRj).0 0100 SUB , Function: Subtract Description: Subtracts the specified variable from the destination operand, leaving the result in the destination operand. SUB sets the CY (borrow) flag if a borrow is needed for bit 7. Otherwise, CY is clear.
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SUB (Rmd) ← (Rmd) – (Rms) SUB WRjd,WRjs Binary Mode Source Mode Bytes: 3 2 States: 3 2 [Encoding] 1001 1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SUB (WRjd) ← (WRjd) – (WRjs) tttt TTTT uuuu UUUU ssss 0000 SUB DRkd,DRks Binary Mode Source Mode Bytes: 3 2 States: 5 4 [Encoding] 1001 1111 Hex Code in: Binary Mode = [A5][En
INSTRUCTION SET REFERENCE [Encoding] 1001 Hex Code in: Operation: 1110 tttt 0100 #data hi #data low 1000 #data hi #data low Binary Mode = [A5][Encoding] Source Mode = [Encoding] SUB (WRj) ← (WRj) – #data16 SUB DRk,#data16 Binary Mode Source Mode Bytes: 5 4 States: 6 5 [Encoding] 1001 1110 uuuu Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SUB (DRk) ← (DRk) – #data16 SUB Rm,dir8 Binary Mode Source Mode Bytes: 4 3 States: 3† 2† †If this instru
8XC251SA, SB, SP, SQ USER’S MANUAL SUB Rm,dir16 Binary Mode Source Mode Bytes: 5 4 States: 3 2 [Encoding] 1001 1110 ssss Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SUB (Rm) ← (Rm) – (dir16) 0011 direct addr direct addr 0111 direct addr direct addr 1001 ssss SUB WRj,dir16 Binary Mode Source Mode Bytes: 5 4 States: 4 3 [Encoding] 1001 1110 tttt Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SUB (WRj) ← (WRj
INSTRUCTION SET REFERENCE [Encoding] 1001 1110 uuuu 1011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SUB (Rm) ← (Rm) – ((DRk)) ssss 0000 SUBB A, Function: Subtract with borrow Description: SUBB subtracts the specified variable and the CY flag together from the accumulator, leaving the result in the accumulator. SUBB sets the CY (borrow) flag if a borrow is needed for bit 7, and clears CY otherwise.
8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 1001 0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: SUBB (A) ← (A) – (CY) – #data immed. data SUBB A,dir8 Binary Mode Source Mode Bytes: 2 2 States: 1† 1† †If this instruction addresses a port (Px, x = 0–3), add 1 state.
INSTRUCTION SET REFERENCE SWAP A Function: Swap nibbles within the accumulator Description: Interchanges the low and high nibbles (4-bit fields) of the accumulator (bits 3–0 and bits 7– 4). This operation can also be thought of as a 4-bit rotate instruction. Flags: Example: CY AC OV N Z — — — — — The accumulator contains 0C5H (11000101B). After executing the instruction SWAP A the accumulator contains 5CH (01011100B).
8XC251SA, SB, SP, SQ USER’S MANUAL Binary Mode Source Mode Bytes: 2 1 States (2 bytes): 11 10 States (4 bytes): 16 15 [Encoding] 1011 1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: TRAP SP ← SP – 2 (SP) ← PC PC ← (0FF007BH) XCH A, Function: Exchange accumulator with byte variable Description: Loads the accumulator with the contents of the specified variable, at the same time writing the original accumulator contents to the specified variable.
INSTRUCTION SET REFERENCE XCH A,@Ri Binary Mode Source Mode Bytes: 1 2 States: 4 5 [Encoding] 1100 011i Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: XCH (A) → ← ((Ri)) XCH A,Rn Binary Mode Source Mode Bytes: 1 2 States: 3 4 [Encoding] 1100 1rrr Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: XCH (A) → ← (Rn) Variations XCHD A,@Ri Function: Exchange digit Description: Exchanges the low nibble of the accumulator (
8XC251SA, SB, SP, SQ USER’S MANUAL Binary Mode Source Mode Bytes: 1 2 States: 4 5 [Encoding] 1101 011i Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: XCHD (A).3:0 → ← ((Ri)).3:0 XRL , Function: Logical Exclusive-OR for byte variables Description: Performs the bitwise logical Exclusive-OR operation (∀) between the specified variables, storing the results in the destination.
INSTRUCTION SET REFERENCE [Encoding] Hex Code in: Operation: 0110 0010 direct addr Binary Mode = [Encoding] Source Mode = [Encoding] XRL (dir8) ← (dir8) ∀ (A) XRL dir8,#data Binary Mode Source Mode Bytes: 3 3 States: 3† 3† †If this instruction addresses a port (Px, x = 0–3), add 1 state. [Encoding] 0110 0011 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: XRL (dir8) ← (dir8) ∀ #data direct addr immed.
8XC251SA, SB, SP, SQ USER’S MANUAL XRL A,@Ri Binary Mode Source Mode Bytes: 1 2 States: 2 3 [Encoding] 0110 011i Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: XRL (A) ← (A) ∀ ((Ri)) XRL A,Rn Binary Mode Source Mode Bytes: 1 2 States: 1 2 [Encoding] 0110 1rrr Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: XRL (A) ← (A) ∀ (Rn) XRL Rmd,Rms Binary Mode Source Mode Bytes: 3 2 States: 2 1 [Encoding] 0110 1100
INSTRUCTION SET REFERENCE Operation: XRL (WRds) ← (WRjd) ∀ (WRjs) XRL Rm,#data Binary Mode Source Mode Bytes: 4 3 States: 3 2 [Encoding] 0110 1110 ssss Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: XRL (Rm) ← (Rm) ∀ #data 0000 #data XRL WRj,#data16 Binary Mode Source Mode Bytes: 5 4 States: 4 3 [Encoding] 0110 1110 tttt 0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: XRL (WRj) ← (WRj) ∀ #data16 #data hi
8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: XRL (WRj) ← (WRj) ∀ (dir8) XRL Rm,dir16 Binary Mode Source Mode Bytes: 5 4 States: 3 2 [Encoding] 0110 1110 ssss Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: XRL (Rm) ← (Rm) ∀ (dir16) 0011 direct addr dir8 addr 0111 direct addr direct addr 1001 ssss \XRL WRj,dir16 Binary Mode Source Mode Bytes: 5 4 States: 4 3 [Encoding] 0110 1
INSTRUCTION SET REFERENCE XRL Rm,@Drk Binary Mode Source Mode Bytes: 4 3 States: 4 3 [Encoding] 0110 1110 uuuu Hex Code In: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: XRL (Rm) ← (Rm) ∀ ((DRk)) 1011 ssss 0000 A-137
B Signal Descriptions
APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the external signals of the 8XC251Sx. pin assignments are shown in Figures B-1 (PLCC package) and B-2 (DIP package) and are listed by functional category in Table B-1. 6 5 4 3 2 1 44 43 42 41 40 P1.4 / CEX1 P1.3 / CEX0 P1.2 / ECI P1.1 / T2EX P1.0 / T2 VSS1 VCC AD0 / P0.0 AD1 / P0.1 AD2 / P0.2 AD3 / P0.3 Table B-2 describes each of the signals.
8XC251SA, SB, SP, SQ USER’S MANUAL Table B-1. PLCC/DIP Pin Assignments Listed by Functional Category Address & Data Name Input/Output PLCC DIP AD0/P0.0 43 39 P1.0/T2 AD1/P0.1 42 38 P1.1/T2EX 3 2 AD2/P0.2 41 37 P1.2/ECI 4 3 AD3/P0.3 40 36 P1.3/CEX0 5 4 AD4/P0.4 39 35 P1.4/CEX1 6 5 AD5/P0.5 38 34 P1.5/CEX2 7 6 AD6/P0.6 37 33 P1.6/CEX3/WAIT# 8 7 AD7/P0.7 36 32 P1.7/CEX4/A17WCLK 9 8 A8/P2.0 24 21 P3.0/RXD 11 10 PLCC DIP 2 1 A9/P2.1 25 22 P3.
SIGNAL DESCRIPTIONS P1.0 / T2 1 40 VCC P1.1 / T2EX 2 39 AD0 / P0.0 P1.2 / ECI 3 38 AD1 / P0.1 P1.3 / CEX0 4 37 AD2 / P0.2 P1.4 / CEX1 5 36 AD3 / P0.3 P1.5 / CEX2 6 35 AD4 / P0.4 P1.6 / CEX3 / WAIT# 7 34 AD5 / P0.5 P1.7 / CEX4 / A17 / WCLK 8 33 AD6 / P0.6 RST 9 32 P3.0 / RXD 10 31 AD7 / P0.7 EA# / VPP 8XC251SA 8XC251SB 8XC251SP 8XC251SQ P3.1 / TXD 11 30 ALE / PROG# P3.2 / INT0# 12 29 PSEN# P3.3 / INT1# 13 28 A15 / P2.7 P3.4 / T0 14 27 A14 / P2.6 P3.
8XC251SA, SB, SP, SQ USER’S MANUAL Table B-2. Signal Descriptions (Continued) Signal Name Alternate Function Type Description I/O Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. P1.5:3 P1.6/WAIT# P1.7/A17/WCLK EA# I External Access. Directs program memory accesses to on-chip or off-chip code memory. For EA# = 0, all program memory accesses are off-chip.
SIGNAL DESCRIPTIONS Table B-2. Signal Descriptions (Continued) Signal Name RST Type Description I Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This signal has a Schmitt trigger input. Connecting the RST pin to VCC through a capacitor provides power-on reset.
8XC251SA, SB, SP, SQ USER’S MANUAL Table B-2. Signal Descriptions (Continued) Signal Name Alternate Function Type Description GND Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP.) — WAIT# I Real-time Wait State Input.
SIGNAL DESCRIPTIONS Table B-3. Memory Signal Selections (RD1:0) RD1:0 P1.7/CEX/ A17/WCLK P3.7/RD#/A16/ PSEN# WR# Features 0 0 A17 A16 Asserted for all addresses Asserted for writes to all memory locations 256-Kbyte external memory 0 1 P1.7/CEX4/ WCLK A16 Asserted for all addresses Asserted for writes to all memory locations 128-Kbyte external memory 1 0 P1.7/CEX4/ WCLK P3.7 only Asserted for all addresses Asserted for writes to all memory locations 64-Kbyte external memory.
C Registers
APPENDIX C REGISTERS This appendix is a reference source of information for the 8XC251Sx special function registers (SFRs) and the register file. The SFR map in Table C-1 provides the address and reset value for each SFR. Tables C-2 through C-6 list the SFRs by functional category. Table C-7 lists the registers that make up the register file. The remainder of the appendix contains descriptions of the SFRs arranged in alphabetical order. For additional information see section 3.
8XC251SA, SB, SP, SQ USER’S MANUAL Table C-1.
REGISTERS Table C-2.
8XC251SA, SB, SP, SQ USER’S MANUAL Table C-4. Serial I/O SFRs Mnemonic Name Address SCON Serial Control S:98H SBUF Serial Data Buffer S:99H SADEN Slave Address Mask S:B9H SADDR Slave Address S:A9H Table C-5.
REGISTERS Table C-6.
8XC251SA, SB, SP, SQ USER’S MANUAL Table C-7. Register File Mnemonic Address R0 – R7 Four banks of 8 registers. Select bank 0-3 with bits RS1:0 of PSW. 1, 2 R8 – R31 R11 = Accumulator (ACC) R10 = B Register. 1, 3 R32 – R55 Reserved R56 – R63 DR56 = the extended data pointer (DPXL, DPH, DPL). DR60 = the extended stack pointer (SPH, SPL). 3 1, 3 NOTE: 1. The registers in the register file are normally accessed by mnemonic.
REGISTERS Address: Reset State: ACC E0H 0000 0000B Accumulator. ACC provides SFR access to the accumulator, which resides in the register file as byte register R11 (also named ACC). Instructions in the MCS® 51 architecture use the accumulator as both source and destination for calculations and moves. Instructions in the MCS 251 architecture assign no special significance to R11. These instructions can use byte registers Rm (m = 0–15) interchangeably.
8XC251SA, SB, SP, SQ USER’S MANUAL CCAPxH, CCAPxL (x = 0–4) Address: CCAP0H,L CCAP1H,L CCAP2H,L CCAP3H,L CCAP4H,L S:FAH, S:EAH S:FBH, S:EBH S:FCH, S:ECH S:FDH, S:EDH S:FEH, S:EEH Reset State: XXXX XXXXB PCA Module Compare/Capture Registers. These five register pairs store the 16-bit comparison value or captured value for the corresponding compare/capture modules. In the PWM mode, the low-byte register controls the duty cycle of the output waveform.
REGISTERS Address: CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 CCAPMx (x = 0–4) S:DAH S:DBH S:DCH S:DDH S:DEH Reset State: X000 0000B PCA Compare/Capture Module Mode Registers. These five registers select the operating mode of the corresponding compare/capture module. Each register also contains an enable interrupt bit (ECCFx) for generating an interrupt request when the module’s compare/capture flag (CCFx in the CCON register) is set. See Table 9-3 on page 9-14 for mode select bit combinations.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: CCON S:D8H 00X0 0000B PCA Timer/Counter Control Register. Contains the run control bit and overflow flag for the PCA timer/counter, and the compare/capture flags for the five PCA compare/capture modules. 7 0 CF Bit Number 7 CR — CCF4 Bit Mnemonic CF CCF3 CCF2 CCF1 CCF0 Function PCA Timer/Counter Overflow Flag: Set by hardware when the PCA timer/counter rolls over.
REGISTERS Address: Reset State: CMOD S:D9H 00XX X000B PCA Timer/Counter Mode Register. Contains bits for selecting the PCA timer/counter input, disabling the PCA timer/counter during idle mode, enabling the PCA WDT reset output (module 4 only), and enabling the PCA timer/counter overflow interrupt. 7 0 CIDL Bit Number 7 WDTE — — Bit Mnemonic CIDL — CPS1 CPS0 ECF Function PCA Timer/Counter Idle Control: CIDL = 1 disables the PCA timer/counter during idle mode.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: DPH S:83H 0000 0000B Data Pointer High. DPH provides SFR access to register file location 58 (also named DPH). DPH is the upper byte of the 16-bit data pointer, DPTR. Instructions in the MCS® 51 architecture use DPTR for data moves, code moves, and for a jump instruction (JMP @A+DPTR). See also DPL and DPXL. 7 0 DPH Contents Bit Number 7:0 Bit Mnemonic DPH.7:0 Function Data Pointer High: Bits 8–15 of the extended data pointer, DPX (DR56).
REGISTERS Address: Reset State: DPXL S:84H 0000 0001B Data Pointer Extended Low. DPXL provides SFR access to register file location 57 (also named DPXL). Location 57 is the lower byte of the upper word of the extended data pointer, DPX = DR56, whose lower word is the 16-bit data pointer, DPTR. See also DPH and DPL. 7 0 DPXL Contents Bit Number 7:0 Bit Mnemonic DPXL.7:0 Function Data Pointer Extended Low: Bits 16–23 of the extended data pointer, DPX (DR56).
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: IE0 S:A8H 0000 0000B Interrupt Enable Register 0. IE0 contains two types of interrupt enable bits. The global enable bit (EA) enables/disables all of the interrupts, except the TRAP interrupt, which is always enabled. The remaining bits enable/disable the other individual interrupts.
REGISTERS Address: Reset State: IPH0 S:B7H X000 0000B Interrupt Priority High Control Register 0. IPH0, together with IPL0, assigns each interrupt a priority level from 0 (lowest) to 3 (highest): IPH0.x IPL0.x Priority Level 0 0 0 (lowest priority) 0 1 1 1 0 2 1 1 3 (highest priority) 7 0 — Bit Number IPH0.6 IPH0.5 IPH0.4 IPH0.3 Bit Mnemonic IPH0.2 IPH0.1 IPH0.0 Function 7 — Reserved. The value read from this bit is indeterminate. Write a zero to this bit. 6 IPH0.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: IPL0 S:B8H X000 0000B Interrupt Priority Low Control Register 0. IPL0, together with IPH0, assigns each interrupt a priority level from 0 (lowest) to 3 (highest): IPH0.x IPL0.x Priority Level 0 0 0 (lowest priority) 0 1 1 1 0 2 1 1 3 (highest priority) 7 0 — Bit Number IPL0.6 IPL0.5 IPL0.4 IPL0.3 Bit Mnemonic IPL0.2 IPL0.1 IPL0.0 Function 7 — Reserved. The value read from this bit is indeterminate.
REGISTERS Address: Reset State: P0 S:80H 1111 1111B Port 0. P0 is the SFR that contains data to be driven out from the port 0 pins. Read-modify-write instructions that read port 0 read this register. The other instructions that read port 0 read the port 0 pins. When port 0 is used for an external bus cycle, the CPU always writes FFH to P0, and the former contents of P0 are lost. 7 0 P0 Contents Bit Number 7:0 Bit Mnemonic P0.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: P2 S:A0H 1111 1111B Port 2. P2 is the SFR that contains data to be driven out from the port 2 pins. Read-modify-write instructions that read port 2 read this register. Other instructions that read port 2 read the port 2 pins. 7 0 P2 Contents Bit Number 7:0 Bit Mnemonic P2.7:0 Function Port 2 Register: Write data to be driven onto the port 2 pins to these bits. Address: Reset State: P3 S:B0H 1111 1111B Port 3.
REGISTERS Address: Reset State: PCON S:87H 00XX 0000B Power Control Register. Contains the power off flag (POF) and bits for enabling the idle and powerdown modes. Also contains two general-purpose flags and two bits that control serial I/O functions—the double baud rate bit and a bit that selects whether accesses to SCON.7 are to the FE bit or the SM0 bit.
8XC251SA, SB, SP, SQ USER’S MANUAL . Address: Reset State: PSW S:D0H 0000 0000B Program Status Word. PSW contains bits that reflect the results of operations, bits that select the register bank for registers R0–R7, and two general-purpose flags that are available to the user. 7 0 CY Bit Number 7 AC F0 RS1 RS0 Bit Mnemonic CY OV UD P Function Carry Flag: The carry flag is set by an addition instruction (ADD, ADDC) if there is a carry out of the MSB.
REGISTERS Address: Reset State: PSW1 S:D1H 0000 0000B Program Status Word 1. PSW1 contains bits that reflect the results of operations and bits that select the register bank for registers R0–R7. 7 0 CY AC Bit Number N RS1 Bit Mnemonic RS0 OV Z — Function 7 CY Carry Flag: 6 AC Auxiliary Carry Flag: Identical to the CY bit in the PSW register. Identical to the AC bit in the PSW register.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: SADDR S:A9H 0000 0000B Slave Individual Address Register. SADDR contains the device’s individual address for multiprocessor communication. 7 0 Slave Individual Address Bit Number 7:0 C-22 Bit Mnemonic SADDR.
REGISTERS Address: Reset State: SADEN S:B9H 0000 0000B Mask Byte Register. This register masks bits in the SADDR register to form the device’s given address for multiprocessor communication. 7 0 Mask for SADDR Bit Number 7:0 Bit Mnemonic Function SADEN.7:0 Address: S:99H Reset State: XXXX XXXXB SBUF Serial Data Buffer. Writing to SBUF loads the transmit buffer of the serial I/O port. Reading SBUF reads the receive buffer of the serial I/O port.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: SCON 98H 0000 0000B Serial Port Control Register. SCON contains serial I/O control and status bits, including the mode select bits and the interrupt flag bits. 7 0 FE/SM0 Bit Number 7 SM1 SM2 REN Bit Mnemonic FE TB8 RB8 TI RI Function Framing Error Bit: To select this function, set the SMOD0 bit in the PCON register. Set by hardware to indicate an invalid stop bit. Cleared by software, not by valid frames.
REGISTERS Address: Reset State: SCON 98H 0000 0000B Serial Port Control Register. SCON contains serial I/O control and status bits, including the mode select bits and the interrupt flag bits. 7 0 FE/SM0 Bit Number 1 SM1 SM2 REN TB8 Bit Mnemonic TI RB8 TI RI Function Transmit Interrupt Flag Bit: Set by the transmitter after the last data bit is transmitted. Cleared by software. 0 RI Receive Interrupt Flag Bit: Set by the receiver after the last data bit of a frame has been received.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: SPH S:BEH 0000 0000B Stack Pointer High. SPH provides SFR access to location 62 in the register file (also named SPH). SPH is the upper byte of the lower word of DR60, the extended stack pointer (SPX). The extended stack pointer points to the current top of stack. When a byte is saved (PUSHed) on the stack, SPX is incremented, and then the byte is written to the top of stack.
REGISTERS Address: Reset State: T2CON S:C8H 0000 0000B Timer 2 Control Register. Contains the receive clock, transmit clock, and capture/reload bits used to configure timer 2. Also contains the run control bit, counter/timer select bit, overflow flag, external flag, and external enable for timer 2. 7 0 TF2 Bit Number 7 EXF2 RCLK TCLK EXEN2 Bit Mnemonic TF2 TR2 C/T2# CP/RL2# Function Timer 2 Overflow Flag: Set by timer 2 overflow. Must be cleared by software.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: T2MOD S:C9H XXXX XX00B Timer 2 Mode Control Register. Contains the timer 2 down count enable and clock-out enable bits for timer 2 . 7 0 — Bit Number 7:2 — — — Bit Mnemonic — — — T2OE DCEN Function Reserved: The values read from these bits are indeterminate. Write zeros to these bits. 1 T2OE Timer 2 Output Enable Bit: In the timer 2 clock-out mode, connects the programmable clock output to external pin T2.
REGISTERS Address: Reset State: TCON S:88H 0000 0000B Timer/Counter Control Register. Contains the overflow and external interrupt flags and the run control and interrupt transition select bits for timer 0 and timer 1. 7 0 TF1 Bit Number 7 TR1 TF0 TR0 IE1 Bit Mnemonic TF1 IT1 IE0 IT0 Function Timer 1 Overflow Flag: Set by hardware when the timer 1 register overflows. Cleared by hardware when the processor vectors to the interrupt routine.
8XC251SA, SB, SP, SQ USER’S MANUAL Address: Reset State: TMOD S:89H 0000 0000B Timer/Counter Mode Control Register. Contains mode select, run control select, and counter/timer select bits for controlling timer 0 and timer 1. 7 0 GATE1 Bit Number 7 C/T1# M11 M01 GATE0 Bit Mnemonic GATE1 C/T0# M10 M00 Function Timer 1 Gate: When GATE1 = 0, run control bit TR1 gates the input signal to the timer register. When GATE1 = 1 and TR1 = 1, external signal INT1 gates the timer input.
REGISTERS TH0, TL0 Address: TH0 S:8CH TL0 S:8AH Reset State: 0000 0000B TH0, TL0 Timer Registers. These registers operate in cascade to form the 16-bit timer register in timer 0 or separately as 8-bit timer/counters. 7 0 High/Low Byte of Timer 0 Register Bit Number 7:0 Bit Mnemonic Function TH0.7:0 High byte of the timer 0 timer register. TL0.7:0 Low byte of the timer 0 timer register. TH1, TL1 Address: TH1 S:8DH TL1 S:8BH Reset State: 0000 0000B TH1, TL1 Timer Registers.
8XC251SA, SB, SP, SQ USER’S MANUAL TH2, TL2 Address: TH2 S:CDH TL2 S:CCH Reset State: 0000 0000B TH2, TL2 Timer Registers. These registers operate in cascade to form the 16-bit timer register in timer 2. 7 0 High/Low Byte of Timer 2 Register Bit Number 7:0 Bit Mnemonic Function TH2.7:0 High byte of the timer 2 timer register. TL2.7:0 Low byte of the timer 2 timer register. Address: Reset State: WCON S:A7H XXXX XX00B Wait State Control Register.
REGISTERS Address: S:A6H Reset State: XXXX XXXXB WDTRST Watchdog Timer Reset Register. Writing the two-byte sequence 1EH-E1H to the WDTRST register clears and enables the hardware WDT. The WDTRST register is a write-only register. Attempts to read it return FFH. The WDT itself is not read or write accessible. See section 8.7, “Watchdog Timer.” 7 0 WDTRST Contents (Write-only) Bit Number 7:0 Bit Mnemonic WDTRST.7:0 Function Provides user control of the hardware WDT.
Glossary
GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this manual. (Chapter 1, “Guide to this Manual,” discusses notational conventions and general terminology.) #0data16 A 32-bit constant that is immediately addressed in an instruction. The upper word is filled with zeros. #1data16 A 32-bit constant that is immediately addressed in an instruction. The upper word is filled with ones. #data An 8-bit constant that is immediately addressed in an instruction.
8XC251SA, SB, SP, SQ USER’S MANUAL big endien form Memory storage format in which the most significant byte (MSB) of the word or double word is stored in the memory byte specified in the instruction. The remaining bytes are stored at higher addresses, with the least significant byte (LSB) at the highest address. binary-code compatibility The ability of an MCS® 251 microcontroller to execute, without modification, binary code written for an MCS 51 microcontroller.
GLOSSARY deassert The term deassert refers to the act of making a signal inactive (disabled). The polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To deassert RD# is to drive it high; to deassert ALE is to drive it low. doping The process of introducing a periodic table Group III or Group V element into a Group IV element (e.g., silicon). A Group III impurity (e.g.
8XC251SA, SB, SP, SQ USER’S MANUAL interrupt handler The module responsible for handling interrupts that are to be serviced by user-written interrupt service routines. interrupt latency The delay between an interrupt request and the time when the first instruction in the interrupt service routine begins execution. interrupt response time The time delay between an interrupt request and the resulting break in the current instruction stream.
GLOSSARY nonpage mode Conventional method for accessing external memory where code fetches require a two-state bus cycle. See also page mode. npn transistor A transistor consisting of one part p-type material and two parts n-type material. OTPROM One-time-programmable read-only memory, a version of EPROM. p-channel FET A field-effect transistor with a p-type conducting path.
8XC251SA, SB, SP, SQ USER’S MANUAL set The term set refers to the value of a bit or the act of giving it a value. If a bit is set, its value is “1”; setting a bit gives it a “1” value. SFR Special-function register. sign extension A method for converting data to a larger format by filling the extra bit positions with the value of the sign. This conversion preserves the positive or negative value of signed integers. sink current Current flowing into a device to ground. Always a positive value.
GLOSSARY word A 16-bit unit of data. In memory, a word comprises two contiguous bytes. wraparound The result of interpreting an address whose hexadecimal expression uses more bits than the number of available address lines. Wraparound ignores the upper address bits and directs access to the value expressed by the lower bits.
Index
INDEX #0data16, A-3 #1data16, A-3 #data definition, A-3 #data16, A-3 #short, A-3 8XC251SA, SB, SP, SQ, 1-1 block diagram, 2-2 on-chip peripherals, 2-3 8XC251Sx, 1-1 8XC51FX, 2-1 A A15:8, 7-1 description, 13-2 A16 description, 13-2 AC flag, 5-18, 5-19, C-20 ACALL instruction, 5-15, A-24, A-26 ACC, 3-13, 3-17, 3-18, C-2, C-3, C-7 Accumulator, 3-15 in register file, 3-13 See also ACC AD7:0, 7-1 description, 13-2 ADD instruction, 5-8, A-14 ADDC instruction, 5-8, A-14 addr11, 5-13, A-3 addr16, 5-13, A-3 addr24,
8XC251SA, SB, SP, SQ USER’S MANUAL CJNE instruction, A-25 Clock, 2-6 external, 11-4, 11-5 external source, 11-3 idle and powerdown modes, 12-5 idle mode, 12-4 powerdown mode, 12-5, 12-6 sources, 11-3 CLR instruction, 5-9, 5-11, A-17, A-23 CMOD, 3-17, 3-19, 9-13, C-2, C-5, C-11 interrupts, 6-5 CMP instruction, 5-8, 5-14, A-15 Code constants, 4-16 Code fetches external, 13-1, 13-5 internal, 13-5 page hit and page miss, 13-6 page mode, 13-6 Code memory MCS 51 architecture, 3-3 See also On-chip code memory, Ex
INDEX ECI, 7-1 EJMP instruction, 5-15, A-24 EMAP# bit, 3-9, 4-16 Encryption, 14-2 Encryption array key bytes, 14-8 programming, 14-1, 14-8 setup for programming, 14-4–14-5 ERET instruction, 5-15, A-24 Escape prefix (A5H), 4-14 Extended stack pointer, See SPX Extending ALE, A-1 extending ALE, A-11 External address lines number of, 4-9 External bus inactive, 13-3 pin status, 13-16, 13-17 structure in page mode, nonpage mode, 13-5 External bus cycles, 13-3 definitions, 13-3 extended ALE wait state, 13-10 exte
8XC251SA, SB, SP, SQ USER’S MANUAL detection, 6-3 edge-triggered, 6-4 enable/disable, 6-5 exiting idle mode, 12-5 exiting powerdown mode, 12-6 external, 6-3, 6-11 global enable, 6-5 instruction completion time, 6-10 latency, 6-9–6-13 level-triggered, 6-4 PCA, 6-5 polling, 6-9, 6-10 priority, 6-1, 6-3, 6-4, 6-7 priority within level, 6-7 processing, 6-9–6-15 request, See Interrupt request response time, 6-9, 6-10 sampling, 6-3, 6-10 serial port, 6-5 service routine (ISR), 6-4, 6-9, 6-14, 6-15 sources, 6-3 t
INDEX N N flag, 5-9, 5-19 Noise reduction, 11-2, 11-3, 11-5 Nonpage mode bus cycles, See External bus cycles, Nonpage mode bus structure, 13-1 configuration, 4-8 design example, 13-22, 13-26 port pin status, 13-16 Nonpage Mode Bus Cycles, 13-4 Nonvolatile memory programming and verifying, 14-1–14-9 NOP instruction, 5-15, A-25 O On-chip code memory, 3-2, 13-8 accessing in data memory, 4-16 accessing in region 00:, 3-9 idle mode, 12-4 powerdown mode, 12-5 programming and verifying, 14-1, 14-7 setup for prog
8XC251SA, SB, SP, SQ USER’S MANUAL Phone numbers, customer support, 1-7 Pin conditions, 12-3 Pins unused inputs, 11-2 Pipeline, 2-5 POP instruction, 3-15, 5-10, A-22 Port 0, 7-2 and top of on-chip code memory, 14-2 pullups, 7-8 structure, 7-3 See also External bus Port 1, 7-2 structure, 7-3 Port 2, 7-2 and top of on-chip code memory, 14-2 structure, 7-4 See also External bus Port 3, 7-2 structure, 7-3 Ports at power on, 11-7 exiting idle mode, 12-5 exiting powerdown mode, 12-5 extended execution times, 5-1
INDEX RETI instruction, 6-1, 6-14, 6-15, A-24 Return instructions, 5-15 RL instruction, A-17 RLC instruction, A-17 ROM (on-chip), 14-1 verifying, 14-1–14-9 See also On-chip code memory, Configuration bytes, Lock bits, Encryption array, Signature bytes.
8XC251SA, SB, SP, SQ USER’S MANUAL T2, 7-1, 8-3 T2CON, 3-17, 3-19, 8-1, 8-2, 8-10, 8-17, 10-13, C2, C-4, C-27 baud rate generator, 10-12 T2EX, 7-1, 8-3, 8-11, 10-12 T2MOD, 3-17, 3-19, 8-1, 8-2, 8-10, 8-16, 13-11, C-2, C-4, C-28 Target address, 5-4 TCON, 3-17, 3-19, 8-1, 8-2, 8-3, 8-6, 8-8, C-2, C4, C-29 interrupts, 6-1 Tech support, 1-7 TH2, TL2 baud rate generator, 10-12, 10-14 THx, TLx (x = 0, 1, 2), 3-17, 3-19, 8-2, C-2, C-4, C-31, C-32 Timer 0, 8-3–8-8 applications, 8-9 auto-reload, 8-5 interrupt, 8-3
INDEX SFR (WDTRST), 3-19, C-4 WCLK (Wait Clock) Output, 13-2 WCON, 3-17, 13-11, C-2, C-3, C-32 WDTRST, 3-17, 3-19, 8-2, 8-16, C-2, C-4, C-33 World Wide Web, 1-7 WR#, 7-1 described, 13-2 X XALE# bit, 4-13 XCH instruction, 5-10, A-22 XCHD instruction, 5-10, A-22 XRL instruction, 5-9 XTAL1, XTAL2, 11-3 capacitance loading, 11-5 Z Z flag, 5-9, 5-19 Index-9