user manual

8XC251SA, SB, SP, SQ USER’S MANUAL
3-2
It is convenient to view the unsegmented, 16-Mbyte memory space as consisting of 256 64-Kbyte
regions, numbered 00: to FF:.
NOTE
The memory space in the MCS 251 architecture is unsegmented. The 64-
Kbyte “regions” 00:, 01:, ..., FF: are introduced only as a convenience for
discussions. Addressing in the MCS 251 architecture is linear; there are no
segment registers.
MCS 251 microcontrollers can have up to 64 Kbytes of on-chip code memory in region FF:. On-
chip data RAM begins at location 00:0000H. The first 32 bytes (00:0000H–00:001FH) provide
storage for a part of the register file. On-chip, general-purpose data RAM begins at 00:0020H.
The sizes of the on-chip code memory and on-chip RAM depend on the particular device.
The register file has its own address space (Figure 3-1). The 64 locations in the register file are
numbered decimally from 0 to 63. Locations 0–7 represent one of four switchable register banks,
each having 8 registers. The 32 bytes required for these banks occupy locations 00:0000H–
00:001FH in the memory space. Register file locations 8–63 do not appear in the memory space.
See “8XC251SA, SB, SP, SQ Register File” on page 3-10 for a further description of the register
file.
The SFR space can accommodate up to 512 8-bit special function registers with addresses
S:000H–S:1FFH. Some of these locations may be unimplemented in a particular device. In the
MCS 251 architecture, the prefix “S:” is used with SFR addresses to distinguish them from the
memory space addresses 00:0000H–00:01FFH. See “Special Function Registers (SFRs)” on page
3-16 for details on the SFR space.
3.1.1 Compatibility with the MCS
®
51 Architecture
The address spaces in the MCS 51 architecture† are mapped into the address spaces in the MCS
251 architecture. This mapping allows code written for MCS 51 microcontrollers to run on MCS
251 microcontrollers. (Chapter 5, “Programming,” discusses the compatibility of the two instruc-
tion sets.)
Figure 3-2 shows the address spaces for the MCS 51 architecture. Internal data memory locations
00H–7FH can be addressed directly and indirectly. Internal data locations 80H–FFH can only be
addressed indirectly. Directly addressing these locations accesses the SFRs. The 64-Kbyte code
memory has a separate memory space. Data in the code memory can be accessed only with the
MOVC instruction. Similarly, the 64-Kbyte external data memory can be accessed only with the
MOVX instruction.
† MCS®51 Microcontroller Family User’s Manual