High Performance Single Board Computer Technical Product Specifications

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Intel NetStructure

MPCBL0001

High Performance Single Board

Computer

Technical Product Specification

May 2006

Order Number: 273817-010

Summary of content (198 pages)

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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Technical Product Specification May 2006 Order Number: 273817-010
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Contents 1 Introduction....................................................................................................................................13 1.1 1.2 2 Features Overview ........................................................................................................................16 2.1 2.2 3 Document Organization .......................................................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 4 E-Keying ............................................................................................................................. 46 IPMC Firmware Code ......................................................................................................... 46 IPMC Firmware Upgrade Procedure ..................................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.16.1 Using Serial Port Buffering ...................................................................................73 3.16.1.1 Configuring the Serial Port.....................................................................73 3.16.1.2 Configuration of Buffering/Filtering ........................................................76 3.16.1.3 Reading Buffered Data ....................................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 BIOS Setup.................................................................................................................................. 116 8.1 8.2 8.3 8.4 8.5 8.6 9 BIOS Error Messages....................................................................................................... 138 Port 80h POST Codes ..............................................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 10.4 10.5 11 Serial Over Lan (SOL) .................................................................................................................151 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 12 Jumpers ............................................................................................................................147 Digital Ground to Chassis Ground Connectivity ...................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 17 Certifications................................................................................................................................ 169 18 Agency Information—Class A...................................................................................................... 170 18.1 18.2 18.3 18.4 18.5 18.6 18.7 19 North America (FCC Class A).............................................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Link Descriptors for E-Keying .....................................................................................................46 Reset BIOS Flash Type ..............................................................................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 93 92 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 10 Supervisor and User Password Functions ............................................................................... 115 Function Key Escape Code Equivalents ..................................................................................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Block Diagram ............................................................................................................................17 Memory Ordering........................................................................................................................22 Hardware Management Block Diagram............................
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Revision History Date 12 Revision Description May 2006 010 Added information related to User Programmable LED and Lead Free information. Added chapter with Serial Over Lan (SOL) information. Added new table (108) listing IPMI 2.0 supported commands. Updated Tables 2, 3, 78, 104 and 106. Added new section (3.14.9) about setting the default color for the OOS and health LEDs.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Introduction 1.1 1 Document Organization This document gives technical specifications related to the Intel NetStructure® MPCBL0001 High Performance Single Board Computer. The MPCBL0001 is designed following the standards of the Advanced Telecommunications Compute Architecture (AdvancedTCA*) Design Guide for high availability, switched network computing.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Chapter 13, “Thermals” contains a graph of pressure drop versus flow rate, illustrating the flow impedance of the slot. Chapter 14, “Component Technology” lists the major components used on the MPCBL0001. Chapter 15, “Warranty Information” provides warranty information for Intel NetStructure® products. Chapter 16, “Customer Support” provides information on how to contact customer support.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents IDE Integrated Device Electronics. Common, low-cost disk interface. IPMB Intelligent Platform Management Bus. Physical 2-wire medium to carry IPMI. IPMC Intelligent Platform Management Controller. ASIC in baseboard responsible for low-level system management. IPMI Intelligent Platform Management Interface. Programming model for system management. KCS Keyboard Controller Style interface. LPC Bus Los Pin Count Bus.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 2 Features Overview 2.1 Application The Advanced Telecommunications Compute Architecture (AdvancedTCA) standards define open architecture modular computing components for carrier-grade, communications network infrastructure.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 1. Block Diagram Optional Optional2.5” 2.5” Hard Hard Disk Disk Drive Drive -48V P10 IPMB-A IPMB IPMB Isolators Isolators IPMB IPMB Isolators Isolators IPMB-B Intel Intel 82802AC 82802AC (FWH0) (FWH0) Intel Intel 82802AC 82802AC (FWH1) (FWH1) SMBUS Standard Standard Microsystems MicrosystemsCorp. Corp.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 2.2.1 Low Voltage Intel® Xeon™ Processor CPU-0 (U35), CPU-1 (U36) The MPCBL0001 SBC supports up to two Low Voltage Intel® Xeon™ processors (see Figure 20, “Component Layout (#1)” on page 100 for locations).
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 2.2.2 Chipset The Intel® E7501 chipset consists of three major components: • Intel® E7501 Memory Controller Hub (MCH) • Intel® 82801CA I/O Controller Hub 3 (ICH3) • Intel® 82870P2 64-bit PCI/PCI-X Controller Hub 2 (P64H2) See Figure 20, “Component Layout (#1)” on page 100 for their locations. 2.2.2.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents • 16-bits wide, 66 MHz clock, 8x data transfer (octal pumped) • Supports 64-bit inbound, 32-bit outbound addressing The MCH I/O subsystems interface incorporates four hub interfaces. Each Hub interface is a pointto-point connection between the MCH and an I/O bridge/device. The various components of the chipset communicate via these connected hub interfaces: • The first hub link connects the MCH to the ICH3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents used. Even though the BIOS automatically sets the DMA mode/type, the OS could downgrade the DMA transfer mode. Check the operating system documentation to see what DMA mode is used by default and whether it is possible to change to a higher performance DMA mode. 2.2.2.3 Intel® 82870P2 64-bit PCI/PCI-X Controller Hub 2 (U14, U24) The two P64H2 devices provide the system’s high-performance PCI bus support.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 2. Memory Ordering Fill Last MCH, U22 J8 Fill First J9 J10 J11 B0894-01 2.2.4 I/O 2.2.4.1 Super I/O (U28) The Super I/O device (SIO) is an SMSC LPC47B272 enhanced Super I/O controller. The SIO connects to the ICH3 through its LPC bus connection. The SIO provides support for the front panel serial port (J17, see page 80). There is no front-panel connection to the legacy keyboard and mouse PS/2 ports.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 2.2.4.2 Real-Time Clock The MPCBL0001 SBC real-time clock is integrated into the ICH3. It is derived from a 32.768 KHz crystal with the following specifications: • • • • Frequency tolerance @ 25 ºC: ±20ppm Frequency stability: maximum of -0.04ppm/(ΔºC)2 Aging ΔF/f (1st year @ 25 ºC): ±3ppm ±20ppm from 0-55 ºC and aging 1ppm/year The real-time clock is powered by a 0.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents • Supports advanced PCI commands such as MWI, MRM, and MRL, and PCI-X commands such as MRD, MRB, and MWB • • • • • 2.2.4.5 Full IEEE 802.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents • Support for JTAG boundary scan. • Supports IP as well as other protocols; however there are currently no plans to validate protocols other than SCSI_FCP. Each Fibre Channel interface of the ISP2312 includes its own internal 16-bit RISC processor and external 7.5 ns synchronous SRAM memory for instruction code and data. Parity protection is provided on accesses to this memory.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Flash ROM BIOS updates can be performed by an end user or a network administrator over the LAN. The system should complete booting to an OS, MS-DOS* or logon to Linux* as root user. The system should have a local copy of the flash program and the BIOS data files or have the capability to copy the flash program and BIOS data files onto a local drive via the network.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 2.2.7 Onboard Power Supplies The main power supply rails on the MPCBL0001 SBC are powered from dual-redundant -48 V power supply inputs from the backplane power connector (P10). There are also dual redundant, limited current, make-last-break-first (MLBF) power connections. See Figure 20, “Component Layout (#1)” on page 100 for their location. 2.2.7.1 Power Feed Fuses As required by the PICMG 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents The VRM controller is designed to support multiple processor core voltages selected by the voltage identification (VID) pins on the processor. Logic provided on the SBC ensures that the VRM is not enabled if the two processors request different VID codes. In addition, the VRM is disabled until all other voltage converters indicate “power good.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3 Hardware Management Overview The Intelligent Platform Management Controller (IPMC) is an Intel-designed baseboard management controller device manufactured by Philips Semiconductor* for Intel. The high-level architecture of the baseboard management for MPCBL0001 is represented in the block diagram below. Figure 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents The IPMC provides six I2C bus connections. Two are used as the redundant IPMB bus connections to the backplane while another one is used for communication with the ADM1026. The remaining buses are unused. If an IPMB bus fault or IPMC failure occurs, IPMB isolators are used to switch and isolate the backplane/system IPMB bus from the faulted SBC board.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 2. Hardware Sensors (Sheet 2 of 3) Sensor Number Sensor Type Voltage/Signals Monitored Monitored via Scanning Enabled under Power State Health LED (Green to Red) 09h Event Logging Disabled BIOS Generated events BIOS SMI Power On No change 10h Voltage 3.3 VSB ADM 1026 Power On/ Off Exceeds critical threshold 11h Voltage +5 VSB ADM 1026 Power On/ Off Exceeds critical threshold 12h +1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 2.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 1 of 4) Sensor Type Code Sensor-Specific Offset (Event Data 1, Bit 0-3) Reserved 00h - Reserved - Temperature 01h - Temperature Threshold exceeded for upper critical, upper noncritical, lower critical and lower non-critical thresholds. Refer to Table 4, “Sensor Thresholds for IPMC Firmware 1.0” on page 37 for sensor thresholds data.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 3. Sensor Type Critical Interrupt SEL Events Supported by the MPCBL0001 SBC (Sheet 3 of 4) Sensor Type Code Sensor-Specific Offset (Event Data 1, Bit 0-3) 13h 04h Event PCI PERR Remarks Event data 2 = Bus No. Event data 3: Byte [7:3] = Device No Byte [2:0] = Func. No 05h PCI SERR Event data 2 = Bus No. Event data 3: Byte [7:3] = Device No Byte [2:0] = Func. No 07h PCI Non-Fatal error Event data 2 = Bus No.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 4. Sensor Thresholds for IPMC Firmware 1.0 Sensor Name Sensor Number System Event Log, reported via CLI, SNMP, RPC, RMCP Normal Value LNR LC LNC UNC UC UNR +1.5 V 1Dh Yes +1.5 V TBD 1.43 1.45 1.55 1.57 – +2.5 V 17h Yes +2.5 V TBD 2.3 2.36 2.625 2.7 – +1.8 V 16h Yes +1.8 V TBD 1.71 1.746 1.854 1.89 – VTT DDR (+1.25 V) 15h Yes +1.25 V TBD 1.185 1.20 1.3 1.315 – +1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 5. Sensor Thresholds for IPMC Firmware 1.2 Thresholds Sensor Name Description Sensor Number Normal Value Lower Critical Lower Noncritical Upper Noncritical Upper Critical Upper Nonrecoverable +1.5V +1.5V 1Dh 1.5 1.43 (1.45) - - 1.57 (1.54) +2.5V +2.5V 17h 2.49 2.29 (2.32) 2.35 (2.375) 2.63 (2.609) 2.69 (2.67) - +1.8V +1.8V 16h 1.79 1.71 (1.73) - - 1.88 (1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 6. Sensor Thresholds for IPMC Firmware 1.7 and Above Thresholds Sensor Name Description Sensor Number Normal Value Lower Critical Lower Noncritical Upper Noncritical Upper Critical Upper Nonrecoverable +1.5V +1.5V 1Dh 1.5 1.43 (1.45) - - 1.57 (1.54) +2.5V +2.5V 17h 2.49 2.29 (2.32) 2.35 (2.375) 2.63 (2.609) 2.69 (2.67) - +1.8V +1.8V 16h 1.79 1.71 (1.73) - - 1.88 (1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 7. Sensor Thresholds for IPMC Firmware 1.14 and Above Thresholds Sensor Name Description Sensor Number Normal Value Lower Critical Lower Noncritical Upper Noncritical Upper Critical Upper Nonrecoverable +1.5V +1.5V 1Dh 1.5 1.43 (1.45) - - 1.57 (1.54) +2.5V +2.5V 17h 2.49 2.29 (2.32) 2.35 (2.375) 2.63 (2.609) 2.69 (2.67) - +1.8V +1.8V 16h 1.79 1.71 (1.73) - - 1.88 (1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.2.2 Processor Events The processor asserts IERR as the result of an internal error. A thermal trip error indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Upon THERMTRIP assertion, the IPMC powers down the boards. 3.2.3 DIMM Memory Events The MCH (E7501) instructs the ICH3 to report memory parity errors via SMI#.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 8 shows the PCI mapping of the component subsystem of the baseboard. Table 8.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.2.6 System ACPI Power State MPCBL0001 is targeted to support ACPI functionality, with support for the sleep states S0, S4 & S5. On assertion of ICH3_SLP_S5# and ICH3_SLP_S3# GPIOs, IPMC sends out a hot-swap event message to the shelf manager requesting deactivation. On successful reception of a deactivation message from the shelf manager, the FRU enters M1 power state and remains in this state.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 9. CPU Failure Behavior CPU Failure Detection CPU Identification Operational Phase POST Runtime 3.2.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.3 Field Replaceable Unit (FRU) Information The FRU Information provides inventory data about the boards where the FRU Information Device is located. The part number or version number can be read through software. FRU information in the MPCBL0001 includes data describing the MPCBL0001 board as per PICMG 3.0 Specification requirements.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.4 E-Keying E-Keying has been defined in the PICMG 3.0 Specification to prevent board damage, prevent misoperation, and verify fabric compatibility. The FRU data contains the board point-to-point connectivity record as described in Section 3.7.2.3 of the PICMG 3.0 Specification. Upon management power-on, the firmware sets the Fibre Channel ports to front panel by default.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents When the firmware is commanded to enter firmware (FW) update mode, the operational code uses a special branch, Software Interrupt, to jump to the FW update code in the boot block. Once in FW update mode, the update code is copied into RAM, then the firmware jumps to the code in RAM to execute. The FW update code cannot execute out of flash while the flash is being updated. Figure 4.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents completed, the controller goes through a reset and boots up with the new firmware. The host processor is not reset when going through a firmware update, so the operating system and applications running on the host processor are not interrupted. Please refer to the latest IPMC firmware release notes for the upgrade procedure.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.7.1 Reset BIOS Flash Type This command resets the processor and changes the BIOS bank select signal so that CPU boots off redundant BIOS bank. Table 13. Reset BIOS Flash Type 7 6 NetFn/LUN 5 3 2 1 NetFn = 3Ah (OEM Request) Command Byte 1 4 0 RsLUN Cmd = 01h BIOS checksum success/failure indication 00h – Checksum success 01h – Checksum failure Byte 1 3.7.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 15. Get Fibre Channel Port Selection 7 6 NetFn/LUN 5 4 2 1 NetFn = 3Ah (OEM Request) Command 0 RsLUN Cmd = 03h Byte 1 Intel IANA number (LSB) = 57h Byte 2 Intel IANA number = 01h Byte 3 Intel IANA number (MSB) = 00h Byte 1 3.7.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 17.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.7.6 Get Control State This command sets the state of a control pin. This command overrides the AUTO-state of the control pin. Refer to Table 20 on page 52 for control number information. Table 18. Get Control State 7 6 NetFn/LUN 5 4 2 1 NetFn = 3Eh (OEM Request) Command 0 RsLUN Cmd = 21h Byte 1 Control number Byte 1 Completion code Byte 2 3.7.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.9 Hot-Swap Process The MPCBL0001 SBC has the ability to be hot-swapped in and out of a chassis. The onboard IPMC manages the SBC’s power-up and power-down transitions. The list below, along with Figure 6, illustrates this process. 1. Ejector latch is opened. HOT_SWAP_PB# assertion. IPMC firmware detects the assertion of this signal. 2. IPMC sends "Deactivation Request" message to CMM. M state moves from M4-> M5. 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.9.1 Hot-Swap LED (DS10) The MPCBL0001 SBC supports one blue Hot Swap LED, mounted on the front panel. See Figure 14, “MPCBL0001NXX SBC Front Panel” on page 81 for its location. This LED indicates when it is safe to remove the SBC from the chassis. The on-board IPMC drives this LED to indicate the hot-swap state. Refer to Table 21, “Hot-Swap LED (DS11)” on page 54.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.10 Interrupts and Error Reporting 3.10.1 Device Interrupts The Low Voltage Intel® Xeon™ processor and E7501 chipset (MCH, ICH3, P64H2) utilize a mechanism for delivering interrupts that is slightly different from, though fully compatible with, previous IA-32 system platforms. The change affects only the delivery mechanism and no changes are required to existing software.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 22. Interrupt Assignments (Sheet 2 of 2) Legacy Interrupt IRQ assigned HI-B P64H2 BTINTR# PIRQC# HI-C P64H2 BTINTR# PIRQD# HI-B P64H2 Fibre Channel INTA# PB_IRQ0 Fibre Channel INTB# PB_IRQ1 HI-C P64H2 Figure 7.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.10.2 Error Reporting The MCH handles error reporting from the memory subsystem. Errors consist of correctable and uncorrectable bit errors. The ECC algorithms used are capable of correcting any number of bit errors contained within a 4-bit nibble. In addition, any number of bit errors contained within two 4bit nibbles is detected. The MCH communicates these errors to the ICH3 via special cycles over the hub link interface.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.11 ACPI ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer. The use of ACPI with theMPCBL0001 SBC requires an operating system that provides ACPI support. ACPI features include: • Plug and Play (including bus and device enumeration) and APM support (normally contained in the BIOS).
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.12.1 Reset Logic The following topics describe the two types of reset requests and the boot relationships among them. The two types of reset requests available on the MPCBL0001 are: • Hard reset request (always results in a cold boot) • Soft reset request (can result in either a warm or cold boot) A hard reset request occurs whenever the processor Reset line is asserted and then deasserted.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 1. The reset button is pressed (see Note below). See Figure 14, “MPCBL0001NXX SBC Front Panel” on page 81 for its location. 2. A processor shutdown special cycle occurred. 3. An INIT command from Port 92h I/O register (refer to the Intel® 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet for information about this register). 4. An INIT command from Port CF9h I/O register. 5. A keyboard reset command (ICH3 RCIN# signal asserted). 6.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.12.5 Cold Boot Any soft reset that does not meet the configuration described in the preceding Warm Boot section is classified as a cold boot. Execution starts at the reset vector, and BIOS initializes and configures all devices, including memory subsystem, as if a hard reset had occurred. See Table 25, “Reset Actions” on page 61.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents As the many voltages power up, each regulator produces a “power good” signal. All of these power good signals are logically OR’d (with the exception of the VRM power good) to produce the ICH3_PWROK signal input to the ICH3 as shown in Figure 8, Power Good Map. When this signal is active, it indicates all on-board power is good.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 9.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.13 Watchdog Timers (WDTs) Figure 10, “Watchdog Timers” on page 64 shows the relationship between the three watchdog timers (WDTs) on the MPCBL0001 SBC. Figure 10. Watchdog Timers ICH3 (South Bridge) WDT #3 Strobe Host Processor(s) Strobe IPMC Strobe WDT #1 PLD WDT #2 IPMB-A Isolation Logic IPMB-B Isolation Logic B1368-02 3.13.1 WDT #1 The first WDT (WDT #1) is a hardware timer in the IPMC.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents WDT #1 can also be configured to take various actions before timing out (for example, SMI, NMI, nothing) or after timing out (for example, hard reset, power down, or power cycle). In addition, an event can be logged into the SEL whenever the watchdog timer expires. If WDT #1 expires, the IPMC is not reset. For more details on the watchdog timer commands and settings, see the IPMI Specification version 1.5.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.14 LED Status 3.14.1 Health LED The MPCBL0001 SBC supports one bicolor health LED to indicate the SBC’s health status, i.e., whether a fault or error condition has been detected on the SBC. This LED is mounted on the front faceplate and driven by the onboard IPMC.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.14.4 IDE Drive Activity LED Table 28. IDE Drive Activity LED LED Status 3.14.5 Meaning Off Normal/No disk access Green (Blinking) Disk access (read/write activity) User Programmable LEDs The MPCBL0001 SBC provides two bicolor LEDs for user-programmable functions. The LEDs can be driven to display a red, green or amber color. When these LEDs are lit, they indicate a status of a user-defined function. Table 29.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.14.6 Network Link/Speed LEDs The front panel of the SBC provides two LEDs for each Ethernet connection indicating the speed and link activity for that network connection: Table 31.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 33. Ethernet Controller Port State LED LED Status (L1 and L5) Meaning Off No Status Red/Green/Amber Active status of user-defined function NOTE: Refer to Figure 14 and Figure 15 for LED (L1 and L5) placement on the Front Panel. 3.14.8 Fibre Channel Port State LEDs The MPCBL0001 SBC supports two Fibre Channel port state LEDs mounted on the front faceplate. The LEDs are green and yellow.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Caution: 3.15 Do not change the Health LED default color to GREEN. Doing so will cause no color change on unhealthy events! FRU Payload Control The MPCBL0001 implements the “FRU Control” command as specified in the PICMG 3.0 Specification. Through this command, the payload can be reset, rebooted, or have its diagnostics initiated.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 11. Flow Diagram for Graceful Reboot Command OS Agent IPMC CMM KCS Interface IPMB Interface Cmmset –l bladex –d frucontrol –v 2 1 2 3 Asserts SMS_ATN signal 4 Get Message 1. MM sends a frucontrol=2 command to IPMC, initiating a graceful reboot. 2. When the IPMC receives frucontrol=2, it formats a message into the send message queue and sets the SMS attention flag (SMS_ATN) on the KCS status register. 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents The implementation details are as below: Figure 12. Diagnostic Interrupt Command Implementation CPU (H_NMI) IPMC CMM GPIO IPMB Interface Cmmset –l bladex –d frucontrol –v 3 1 2 Asserts NMI signal 1. CMM sends a frucontrol=3 command to IPMC initiating a diagnostic interrupt. 2. When the IPMC receives frucontrol=3, it asserts the NMI signal to the CPU via the GPIO pins connected to the H_NMI pin. 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 37. Escape Sequences Not Buffered with Filter Enabled Description PC ANSI Codes Move cursor up 1 row ESC [ A Move cursor down 1 row ESC [ B Move cursor right 1 column ESC [ C Move cursor left 1 column ESC [ D Home ESC [ H End ESC [ K Clear Display Screen ESC [ 2 J Set cursor position to row;col. ESC [ row;col H Set Text Attributes ESC [x;y;z m 3.16.1 Using Serial Port Buffering 3.16.1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 38.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 39.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 3.16.1.2 Configuration of Buffering/Filtering Configuration of the Serial Buffering and Filtering features is accomplished with Intel-specific (OEM) IPMI commands: Set Serial Buffer Configuration and Get Serial Buffer Configuration. The Set Serial Buffer Configuration command can enable/disable both filtering and buffering.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents There is an Intel-specific command to read back the buffer data in chunks of 16 bytes. This command requires a 16 bit offset into the buffer from which to read. System software can invoke this command several times in order to read the entire buffer. A buffer offset of 0 refers to the start of the oldest data in the buffer and not necessarily the physical start of the buffer.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents function PrintUsage() { echo echo "Usage: $0 location" echo echo "Where: location = the location to read from (i.e. blade3, blade13, etc)" echo echo "This program reads the entire Serial Buffer from the selected location" echo "and saves it under file name: \'location\'.txt Ex: blade3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents if [ $# -ne 1 ]; then PrintUsage fi LOC=$1 # Location to read from SEL_FILENAME="$LOC.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 4 Connectors Connectors along the rear edge of AdvancedTCA server blades are divided into three distinct zones, as described in Section 2.3 of the PICMG 3.0 Specification. • Zone 1 for system management and power distribution • Zone 2 for data fabric • Zone 3 for the rear transition module. As shown in Figure 13, the MPCBL0001 includes several connectors to interface with applicationspecific devices.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 14.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 15.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 43. LED Descriptions LED Description Out of Service, bicolor OOS Health, bicolor IDE Drive Activity Lights when drive activity occurs.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 4.1 Backplane Connectors 4.1.1 Power Distribution Connector (Zone 1) Zone 1 consists of P10, a 34-pin Positronic header connector that provides the following signals: • • • • Note: Two -48 VDC power feeds (four signals each; eight signals total) Two IPMB ports (two signals each, four signals total) Geographic address (eight signals) 5.55 Amperes are allocated to MPCBL0001 on the -48 VDC redundant power feeds.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 45.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents P[C]dxp where: P = Prefix (B=Base Interface [Gigabit Ethernet], F= Fabric Interface [Fibre Channel]) C = Channel (1-2) d = direction (Tx = Transmit, Rx = Receive) x = port number (0-1) Note: A port is two differential pairs, one Tx and one Rx p = polarity (+, -) The BG, DG, FG and HG (G for Ground) columns contain the ground shields for the four columns of differential pairs.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 4.2 Front Panel Connectors 4.2.1 USB Connector (J12) MOLEX part Number: 67329-0020 The MPCBL0001 SBC has one vertical USB connector that supports USB 1.1. USB connector JX is available at the front panel, as shown in Figure 13, “MPCBL0001 SBC Connector Locations” on page 80. The figure shows its position on the board. See Table 47, “USB Connector (J12) Pin Assignments” on page 87 for pinout information. Table 47.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 18. Serial Port Connector (J17) Optional Top Ground Tabs Shielded Modular Jack Assembly molex Optional Side Ground tabs (2 places) .512 REF. 13.00 (outside) .120 REF. 3.05 .724 REF. 18.39t .120 REF. 3.05 .120 3.05 .128 3.25 .427 10.85 .829 21.05 B0902-01 Table 48.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 19.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 4.2.3 Fibre Channel Small Form-Factor Pluggable (SFP) Receptacle (J34 and J35) AMP part number: 1367073-1 The MPCBL0001 SBC has two SFP receptacles that support either the copper or fiber module interface. Fibre Channel connector J34 and J35 are available at the front panel. See Figure 13, “MPCBL0001 SBC Connector Locations” on page 80 for its position on the board.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 50. Fibre Channel SFP Pin Assignments USFibre Channel Connector (J34, J35) Pin Assignments Fibre Channel SFP Optical Transceiver Module (J34, J35) Fibre Channel CONNECTOR 4.2.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 51. PMC Connector Pin Assignments - 32 Bit J25 92 32 Bit PCI J26 32 Bit PCI Pin Signal Signal Pin Pin Signal Signal Pin 1 TCK -12 V 2 1 +12 V TRST# 2 3 Ground INTA# 4 3 TMS TDO 4 5 INTB# INTC# 6 5 TDI Ground 6 7 BUSMODE1# +5 V 8 7 Ground PCI-RSVD 8 9 INTD# PCI-RSVD 10 9 PCI-RSVD PCI-RSVD 10 11 Ground (n/c) 3.3 Vaux 12 11 BUSMODE2# +3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 52. PMC Connector Pin Assignments - 64 Bit J27 64 Bit PCI Pin Signal Signal Pin 1 PCI-RSVD Ground 2 3 Ground C/BE[7]# 4 5 C/BE[6]# C/BE[5]# 6 7 C/BE[4]# Ground 8 9 +3.3 V (V I/O) PAR64 10 11 AD[63] AD[62] 12 13 AD[61] Ground 14 15 Ground AD[60] 16 17 AD[59] AD[58] 18 19 AD[57] Ground 20 21 +3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 4.3 On-board Connectors 4.3.1 IDE Connector (J24) Table 53.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 5 Addressing 5.1 Configuration Registers 5.1.1 Configuration Address Register MCH CONFIG_ADDRESS I/O Address: 0x0CF8 Accessed as a Dword Default Value: 0x00000000 Access: Read/Write Size: 32 bits CONFIG_ADDRESS is a 32-bit I/O register that can be accessed only as a Dword. A byte or word reference passes through the Configuration Address Register and hub link interface HI_A onto the PCI_A bus as an I/O cycle.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents CONFIG_DATA is a 32-bit read/write window into the PCI configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Table 55.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 5.3 Memory Map Table 57. Memory Map Memory Device Address Size Top of addressable memory 0xFFFF_FFFF -- Firmware Hub Devices (x2) 0xFFE0_0000 Up to 16 Mbit -- Firmware Hub Device 0 0xFFF0_0000 8 Mbit/1 MB -- Firmware Hub Device 1 0xFFE0_0000 8 Mbit/1 MB ...
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 5.4 IPMC Addresses The IPMC supports 6 I2C/SMB buses. IPMC buses 0 and 1 provide redundant IPMB connections. The ADM1026 device is connected to SMBus 3 and provides voltage measurement capability and additional board configuration status. Table 58.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Specifications 6 This chapter defines the MPCBL0001 operating and nonoperating environments. It also documents the procedures followed to determine the reliability of MPCBL0001. 6.1 Mechanical Specifications 6.1.1 Board Outline Figure 20 and Figure 21 are annotated illustrations of the MPCBL0001 SBC showing the locations of major components. The board dimensions are 280 mm x 322.25 mm. The board pitch is 1.2” (30.48 mm).
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 20. Component Layout (#1) 280 mm IDE Connector (J24) DIMMs J16 PMC Connectors GP2 GP1 322.25 mm 350.93 mm Gigabit Ethernet MCH J23 Intel® Xeon™ Processor Intel® Xeon™ Processor P10 J18 Fibre Channel Bar code: PBA number for the board Bar code: MAC Address 1 B3215-03 NOTE: MAC Address 2 is an incremental value of MAC Address 1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 21. Component Layout (#2) 280 mm GP 2 B A C D 322.25 mm 350.93 mm Ethernet Controller GP 1 E F MCH Fibre Channel Controller G Intel® LV XeonTM 2.0 GHz J 23 Intel® LV XeonTM 2.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 6.1.2 Backing Plate The MPCBL0001 SBC has a rugged metal backing plate that forms a single-piece face plate. This backing plate is made of 1.2 mm (0.048") steel which has been zinc post-plated to resist corrosion and rust. The solid backing plate provides PCB stiffening, enhanced EMI protection from adjacent boards, and protection during flame tests. The backing plate improves serviceability by making the SBC more durable.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 22.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 23.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 24.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 25.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 6.2 Environmental Specifications The MPCBL0001 SBC meets the board-level specifications as specified in the Intel Environmental Standards Handbook – Telco Specification Document No. A78805-01. The test methodology is a combination of Intel and NEBs test requirements with the intent that the product will pass pure system-level NEBs testing. Intel will not be completing NEBs testing on the SBC.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 6.3.1.1 Environmental Assumptions • Failure rates are based on a 40° C ambient temperature. • Applied component stress levels are 50 percent (voltage, current, and/or power). • Ground, fixed, controlled environment with an environmental adjustment factor equal to 1.0. 6.3.1.2 General Assumptions • Component failure rates are constant. • Board-to-system interconnects included within estimates.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 6.3.3 Cooling Requirements The Intel NetStructure® MPCBL0001 High Performance Single Board Computer SBC should be installed vertically in a chassis, with bottom-to-top airflow. Airflow is expected to be evenly distributed across the bottom edge of the installed MPCBL0001 blade and maintain at least 300 LFM average airflow.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 7 BIOS Features 7.1 Introduction The Intel NetStructure® MPCBL0001 High Performance Single Board Computer SBC uses an Intel/AMI BIOS, which is stored in flash memory and updated using a disk-based program. In addition to the BIOS and BIOS setup program, the flash memory contains POST and Plug and Play support. The BIOS displays a message during POST identifying the type of BIOS and a revision code.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents The utility is part of the BIOS release package and can be downloaded from the Intel web site at http://www.intel.com/design/network/products/cbp/software/bios/mpcbl0001.htm. Refer to Chapter 10, “Operating the Unit,” for more information. 7.4 Redundant BIOS Functionality MPCBL0001 hardware has two flash banks for BIOS where redundant copies are stored.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 7.6 Legacy USB Support Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even when the operating system’s USB drivers are not yet available. Legacy USB support is used to access the BIOS Setup program and install an operating system that supports USB. Legacy USB support is set to Enabled by default. Note: Legacy USB support is for keyboards, mice and hubs only.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 7.7.1 Language Support English is the only supported language. 7.8 Recovering BIOS Data Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from Backup BIOS. Recovery mode is active when BIOS checksum fails and notifies the IPMC to failover to the backup BIOS. 7.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 7.10 Fast Booting Systems 7.10.1 Quick Boot Use of the following BIOS Setup program settings reduces the POST execution time. In the Boot Menu: • Disable Option—ROM(s) if the user configuration does not use IBA(PXE) boot, or there is no Fibre Channel drive in the system. • Disable Quiet Boot eliminates display of the logo splash screen.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 62. 7.12 Supervisor and User Password Functions User Mode Password to Enter Setup Password Set Supervisor Mode Password During Boot None Any user can change all options Any user can change all options None None Supervisor and user Can change all options Based on user access level: No Access, View Only, Limited, Full Access Supervisor or user If password check option is set to Setup then no password required.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8 BIOS Setup 8.1 Introduction The BIOS Setup program can be used to view and change the BIOS settings for the computer. The BIOS Setup program is accessed by pressing the key after the Power-On Self-Test (POST) begins and before the operating system boot begins. Table 64 lists the BIOS Setup program menu features. Table 64.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 66. Main Menu Feature Options Description AMIBIOS Version BIOS ID Build Date Displays the BIOS ID. ID Type Processor Speed Reports processor type, speed, CPUID and L2 Cache size. Count System Memory Size Size Displays system memory size. System Time Hour, minute, and second Specifies the current time. Day of week System Date 8.3 Specifies the current date.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 67 describes the Advanced menu. This menu sets advanced features that are available through the chipset. Table 67. Advanced Menu Feature Options Description CPU Configuration Select to display submenu Display CPU details, Enable/Disable Hyper-Threading Technology†. IDE Configuration Select to display submenu Display the primary IDE master and primary IDE slave drive.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents The submenu represented in the following table is used for configuring the CPU. Table 68. CPU Configuration Submenu Feature Options Description Manufacturer Display CPU Manufacturer Brand String Display CPU Brand String Frequency Display CPU Frequency HyperThreading Technology† Enable/Disable Hyper-Threading Technology†. Disabled, Enabled NOTE: Bold text indicates default setting. 8.3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 69. IDE Configuration Submenu (Sheet 2 of 2) Feature Options Hard Disk Write Protect Disabled Enabled Description Enable/Disable Hard Disk device write protection. This is effective only if the device is accessed through BIOS. 0 5 10 15 IDE Detect Time Out 20 Select the time out value for detecting ATA/ATAPI device(s). 25 30 35 Host&Device ATA(PI) 80Pin Cable Detect.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 70. Primary IDE Master/Slave Submenu Feature Options Description Device Display IDE device. Vendor Display IDE vendor name. Size Display IDE device size. LBA Mode Display IDE LBA Mode status. Block Mode Display IDE Block Mode status. PIO Mode Display PIO Mode status. Async DMA Display Async DMA status. Ultra DMA Display Ultra DMA-5 status. S.M.A.R.T Display S.M.A.R.T status.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.3 Floppy Configuration Submenu To access this submenu, select Advanced on the menu bar, then Floppy Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.4 SuperIO Configuration Submenu To access this submenu, select Advanced on the menu bar, then SuperIO Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.5 ACPI Configuration Submenu To access this submenu, select Advanced on the menu bar, then ACPI Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.5.1 Advanced ACPI Configuration Submenu To access this submenu, select Advanced on the menu bar, then ACPI Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.6 System Management Configuration Submenu To access this submenu, select Advanced on the menu bar, then System Management Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.7 Event Logging Configuration Submenu To access this submenu, select Advanced on the menu bar, then Event Logging Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.8 Fibre Channel Routing (PICMG) Configuration Submenu To access this submenu, select Advanced on the menu bar, then Fibre Channel Routing (PICMG) Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.9 Remote Access Configuration Submenu To access this submenu, select Advanced on the menu bar, then Remote Access Configuration.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 78. Remote Access Configuration Submenu (Sheet 2 of 2) Feature Options Disabled VT-UTF8 Combo Key Support Enabled Disabled2 SOL Support Enabled Description Enable VT-UTF8 Combination Key support for ANSI/VT100 terminals. Enable BIOS to automatically redirect the console redirection information to serial port dedicated for SOL when SOL session is active. NOTES: 1. Bold text indicates default setting. 2.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 79. USB Configuration Submenu 10 sec USB Mass Storage Reset Delay 20 sec 30 sec Number of seconds POST waits for USB mass storage device after unit command. 40 sec USB Beep Message Disabled Enabled Enable the beep during USB device enumeration. NOTE: Bold text indicates default setting.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 8.3.10.1 USB Mass Storage Device Configuration Main Advanced Boot Security Exit CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration USB Configuration USB Mass Storage Device Configuration Table 80.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents USB Configuration USB Mass Storage Device Configuration PCI Configuration The menu represented in the following table is used to configure USB options. Table 81. PCI Configuration Submenu Feature Options Disabled Onboard Fibre Channel Enabled Disabled Onboard Gigabit LAN 8.4 Enabled Description Enable/Disable Onboard Fibre Channels Option-ROM.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents The menu represented in the following table is used to configure Boot Settings. Table 83. Boot Settings Configuration Submenu Feature Options Disabled Quick Boot Disable/Enable the BIOS to skip certain tests while booting, to decrease the time needed to boot the system. Enabled Disabled Quiet Boot Display normal POST messaged/OEM logo.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 84. Boot Device Priority Submenu Feature Options Description Hard Drive 1st Boot Device IBA 2 Set the first boot device. IBA 1 2nd Boot Device Same options as first boot device. Set the second boot device. Last Boot Device Same options as first boot device. Set the last boot device. NOTE: A device only shows as an option if it is installed and detected by the BIOS during boot. 8.4.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 86. OS Load Timeout Timer Submenu Feature Options Description Disabled 60sec 120 sec OS Load Timeout 150 sec Select the timeout value for OS load timer. 240 sec 480 sec 600 sec Stay On Reset OS Load Action Controls the action upon timeout. Power Off Power Cycle 8.5 Security Menu To access this menu, select Security from the menu bar at the top of the screen.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents The menu represented in the following table is for exiting the BIOS Setup program, saving changes, and loading and saving defaults. Table 88. Exit Menu Feature Options Description Save Changes and Exit Exit system setup after saving changes. Use this to save your configured settings to the CMOS and Flash. Discard Changes and Exit Exit system setup without saving changes. Discard Changes Discard changes without exiting.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 9 Error Messages 9.1 BIOS Error Messages The following table lists the error messages. Table 89. BIOS Error Messages Error Message Note: Explanation of Error Message Timer Error This timer is based on 8254 resides in ICH-3. Error message indicates an error while programming the count register of the timer.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 2. Clear CMOS Jumper enabled 3. MFG Jumper installed. 9.2 Port 80h POST Codes During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST codes requires an add-in card, often called a POST card (PCI, not ISA).
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 91. POST Code Checkpoints (Sheet 1 of 2) Checkpoint 140 Description 03 Disable NMI, parity, video for EGA, and DMA controllers. Initialize BIOS, POST, runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the kernel variable. 04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 91. POST Code Checkpoints (Sheet 2 of 2) Checkpoint Description 3B Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test. Display total memory in the system. 3C Mid POST initialization of chipset registers. 40 Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA, etc.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 92. DIM Code Checkpoints Checkpoint 2A Description Initializes different buses and performs the following functions: • Function 0: Reset, Detect, and Disable - Disables all device nodes, PCI devices, and PnP ISA cards. Assigns PCI bus numbers.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Operating the Unit 10.1 10 BIOS Configuration See Chapter 7, “BIOS Features,” for BIOS configuration options and Chapter 8, “BIOS Setup,” for information about using the BIOS Setup program. See Section 2.2.3.1, “Memory Ordering Rule for the MCH” on page 21 for information about installing DIMMs. 10.2 BIOS Image Updates At times, new BIOS images will be released to add additional features to the SBC.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 10.3.2 Saving BIOS.bin to the SBC 1. Copy the flashlnx utility and BIOS.bin to the SBC running MontaVista Carrier Grade Linux. 2. Execute “chmod +x flashlnx” to change the file attribute to executable form. 3. Execute “./flashlnx -b -zc BIOS.bin” to copy the BIOS.bin file to the FWH and CMOS. 4. Upon completion, perform a reset to ensure the new CMOS settings and BIOS are loaded. Caution: 10.3.3 To ensure that the BIOS.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 96. Suggested Method of BIOS Image Synchronization prior to BIOS Upgrade BIOS Image Command Behavior This is the original FWH image before an upgrade. FWH0 Image N FWH0 has Image N installed, which is a newer image than what is installed in FWH1 (Image N-1). FWH1 Image N-1 FWH0 Image N ./flashlnx –m When this command is invoked, Image N in FWH0 (BIOS codes + CMOS settings) is synchronized to FWH1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 97.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 10.4 Jumpers The MPCBL0001 contains several jumper posts that allow the user to configure certain options not configurable through the BIOS Setup Utility. The “Jumper Locations” figure below shows the placement of the MPCBL0001 jumpers. See Table 101, “J40 Jumper Assignments” on page 149 for the function of each jumper. Note: Figure 27. The MPCBL0001 is shipped pre-configured—jumper positions do not need to be altered.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 98. J18 Pin Assignments Lattice* Compatible JTAG Header PS/2 Keyboard/Mouse Header 1 +3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Table 101. J40 Jumper Assignments Jumper Function J40-1 to 2 Boot block unprotected. J40-2 to 3 IPMC Boot block has been protected (Default). If user were to update the IPMC boot block, the jumper needs to be connected to 1-2.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Figure 28.
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Serial Over Lan (SOL) Serial Over Lan (SOL) 11 Serial over LAN (SOL) is a packet format and protocol defined in the IPMI v2.0 specification for transmitting serial port data over Ethernet using IPMI over LAN (RMCP+) messages. This twoway redirection of a blade’s serial port data over Ethernet is independent of the operating system or any applications executing on it. The BIOS also supports redirection of its console over serial port, which can be redirected over the network for remote access.
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Serial Over Lan (SOL) Figure 29 is a block diagram of the SOL implementation on the blade: Figure 29. SOL Block Diagram This architecture requires the following three components to perform Serial over LAN operations. 1. SOL capable firmware executing on the Intelligent Platform Management Controller (IPMC). The IPMC also provides a dedicated SMBus connection to base interface Ethernet controller.
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Serial Over Lan (SOL) transformation of serial data to and from network packets, and the transmission and reception of SOL network packets through the Ethernet controller TCO port. 11.2.1 Architectural Components 11.2.1.1 IPMC As shown in the block diagram in Figure 29, the IPMI controller on the blade provides a UART interface to the blade’s serial port (COM2).
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Serial Over Lan (SOL) From the table above, the serial over LAN can only be activated if a user configures the BIOS correctly. By default, the console redirection setting is enabled and the SOL support is set to “Disabled”. If a user has a serial session active via the front panel and a user initiates a SOL session on this blade, the serial data on the front panel will be deactivated automatically. The serial data will be sent via the LAN interface to the SOL client system.
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Serial Over Lan (SOL) The maximum baud rate supported by the IPMC for SOL is 115.2 kbps. There will be a minimal improvement between the baud rate of 19.2kbps to 115.2kbps. This is due to a combination of all the software overhead of creating/breaking down IP packets in the IPMC as well as a slower link between the IPMC and the NIC (I2C). If a user configures the SOL configuration without modifying the reference_cfg file, the default baud rate is 9.6 kbps. Note: 11.4 The BIOS default baud rate is 9.
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Serial Over Lan (SOL) 11.5 Supported Usage Model Customers are expected to use Serial Over LAN to accomplish the following: • BIOS console redirection • As a remote terminal for OS setup and viewing text console output The ipmitool utility runs on a remote network node and communicates over the LAN interface. The remote node and the target SBC may be on the same subnet or on different subnets. The reference script can be run on the remote node. Figure 30.
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Serial Over Lan (SOL) 11.6 Installation and Configuration 11.6.1 SOL Configuration Reference Script (reference_cfg) The reference script can run with no special setup. The script uses built-in bash commands as well as grep and awk. The environment in which the script runs must have bash installed at /bin/bash (or a symbolic link at that location), and must include grep and awk in the path.
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Serial Over Lan (SOL) HostIP = IP address of the ethernet interface on the IPMC (MPCBL0001 blade) that has been configured for SOL access. UserName = User name of an authorized SOL client user. The configuration helper “reference_cfg” creates such a client with UserName = solusername. Password = Password assigned for ‘UserName’. The configuration helper “reference_cfg” assigns Password = soluserpassword for UserName = solusername.
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Serial Over Lan (SOL) 11.7.2 SOL User Information Intel’s SBCs implement four different users, User1 through User4. User1 has null username which is not editable. The script configures User2. User2 is enabled and specifically enabled for SOL payloads. The user name is “solusername”, zero-padded to a length of 16 bytes as per the IPMI specification. The password is “soluserpassword”, zero-padded to 20 bytes as per the IPMI 2.0 extension. 11.7.
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Serial Over Lan (SOL) IP and MAC addresses supplied to the IPMC are specified on the command line as specified in Table 104. IP source is set to “static” and the subnet mask is set for a class C subnet. The Gateway IP and MAC address should be specified in the command to enable RMCP communication across subnets. If the IP or MAC address options are missing from the command line, those parameters will not be changed on the IPMC. If VLAN (802.
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Serial Over Lan (SOL) 11.7.7 Executing the SOL Client (ipmitool) To start a SOL console, a user must first connect with the command: ipmitool -I lanplus -L operator -H -U -P sol activate The first argument given in this command line is the host name or IP address of the system on which ipmitool is running. The next two arguments are the SOL configured username and password on the SBC.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 12 Maintenance 12.1 Supervision There are four main components that perform hardware monitoring of voltages and timers. They are listed in the table below. Table 105. Hardware Monitoring Components Component Function Monitors Intelligent Platform Management Controller WDT #1 Commands from the BIOS. If the timer expires (times out), causes a soft or hard reset. Heceta-5 (ADM1026) Analog-to-Digital Voltages: +1.2 V, +1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Thermals 13 The pressure drop curves versus the flow rate in Figure 31 represents flow impedance of the slot This information is provided in accordance with Section 5 of the PICMG 3.0 Specification. It will aid the system integrator in using the MPCBL0001 SBC in various AdvancedTCA shelves. Figure 31. Power vs.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 14 Component Technology The main components implemented on the Intel NetStructure® MPCBL0001 High Performance Single Board Computer are listed in the table below. Table 106.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Warranty Information 15.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 15.3 For the Americas Return Material Authorization (RMA) credit requests e-mail address: requests.rma@intel.com Direct Return Authorization (DRA) repair requests e-mail address: uspss.repair@intel.com DRA on-line form: http://support.intel.com/support/motherboards/draform.htm Intel Business Link (IBL): http://www.intel.com/ibl Telephone No.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents If the Customer Support Group verifies that the product is defective, they will have the Direct Return Authorization/Return Material Authorization Department issue you a DRA/RMA number to place on the outer package of the product. Intel cannot accept any product without a DRA/RMA number on the package.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 16 Customer Support 16.1 Customer Support This chapter offers technical and sales assistance information for this product. Information on returning an Intel NetStructure® product for service is in the following chapter. 16.2 Technical Support and Return for Service Assistance For all product returns and support issues, please contact your Intel product distributor or Intel Sales Representative for specific information. 16.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Certifications 17 The Intel NetStructure® MPCBL0001 High Performance Single Board Computer has the following approvals: • • • • • • UL/cUL 60950 EN/IEC 60950 EN55024 VCCI AS/NZS3548 BSMI For the The Intel NetStructure® MPCBL0001N04 Single Board Computer and Intel NetStructure® MPCBL0001F04 Single Board Computer, all boards with the TA# C13354-010 and C55360-011 (or below) respectively have the following approvals: • EN55022
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Agency Information—Class A 18.1 18 North America (FCC Class A) FCC Verification Notice This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents -This equipment shall be connected directly to the DC supply system earthing electrode conductor or to a bonding jumper from an earthing terminal bar or bus to which the DC supply system earthing electrode conductor is connected.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 18.5 Japan VCCI Class A 18.6 Korean Class A 18.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Agency Information—Class B 19.1 19 North America (FCC Class B) FCC Verification Notice This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents -This equipment shall be connected directly to the DC supply system earthing electrode conductor or to a bonding jumper from an earthing terminal bar or bus to which the DC supply system earthing electrode conductor is connected.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 19.5 Korean Class B 19.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 20 Safety Warnings Caution: Review the following precautions to avoid personal injury and prevent damage to this product or products to which it is connected. To avoid potential hazards, use the product only as specified.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Warning: Avoid electric shock: Do not operate in wet, damp, or condensing conditions. To avoid electric shock or fire hazard, do not operate this product with enclosure covers or panels removed. Warning: Avoid electric shock: For units with multiple power sources, disconnect all external power connections before servicing. Warning: Power supplies must be replaced by qualified service personnel only.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Pour les systèmes C.A., utilisez uniquement un câble d'alimentation avec une prise de terre et établissez toujours les connexions à une prise secteur mise à la terre. Chaque câble d'alimentation doit être connecté à un circuit terminal dédié. Pour les systèmes C.C., la protection de cette unité repose sur les coupe-circuits (surintensité) du bâtiment.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents ventilateur ou les conduits de l'unité. Des boucliers ou des panneaux de gestion de l'air doivent être installés dans les connecteurs inutilisés du châssis. Les spécifications environnementales peuvent varier d'un produit à un autre. Veuillez-vous reporter au manuel de l'utilisateur pour déterminer les exigences en matière de flux d'air et d'autres spécifications environnementales.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Das Gehäuse verfügt über einen eigenen Erdungs-Verbindungsbolzen. Stellen Sie die Erdungsverbindung her, ehe Sie das Stromkabel oder Peripheriegeräte anschließen, und trennen Sie die Erdungsverbindung niemals, so lange Strom- und Peripherieverbindungen angeschlossen sind.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Vorsicht: Lithiumbatterien. Bei unsachgemäßem Austausch oder Umgang mit Batterien besteht Explosionsgefahr. Zerlegen Sie die Batterie nicht und laden Sie diese nicht wieder auf. Entsorgen Sie die Batterie nicht durch Verbrennen. Beim Auswechseln der Batterie muss dasselbe oder ein der Händlerempfehlung gleichwertiges Modell verwendet werden (CR2032).
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents NORME DI SICUREZZA PER LE UNITÀ MONTATE IN UN RACK. Questa unità può essere alloggiata in modo permanente in un rack. Il montaggio in rack deve essere conforme ai requisiti di resistenza fisica delle norme NEBS GR-63-CORE e NEBS GR 487.Prima di installare o rimuovere l'unità da un rack, rimuovere tutte le fonti di alimentazione e i collegamenti esterni.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 20.4 Instrucciones de Seguridad Examine las instrucciones sobre condiciones de seguridad que siguen para evitar cualquier tipo de daños personales, así como para evitar perjudicar el producto o productos a los que esté conectado. Para evitar riesgos potenciales, utilice el producto únicamente en la forma especificada.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Advertencia: Evite sobrecargas eléctricas, calor y riesgos de descarga eléctrica o incendio: Conecte el sistema sólo a un circuito de alimentación que tenga el régimen apropiado, según lo especificado en el manual de usuario del producto. No realice conexiones con terminales cuya capacidad no se ajuste al régimen especificado para ellos.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 20.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents Reference Documents A The following documents should be available when using this specification. Documents that are not available on websites may be obtained from your IBL (Intel Business Link) account, or contact your Intel Field Sales Engineer (FSE) or Field Application Engineer (FAE). • Qlogic* ISP2312 Intelligent Fibre Channel Processor data Sheet, 83312-508-00 B, March 19, 2002 (http://www.qlogic.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents • Low Pin Count (LPC) Interface Specification (http://developer.intel.com/design/chipsets/ industry/lpc.htm) • Intel® Boot Agent. (http://www.intel.com/support/network/adapter/pro100/bootagent/ manual.htm) • Intel’s AdvancedTCA product line http://developer.intel.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Contents 188 Technical Product Specification Order #273817
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer List of Supported Commands (IPMI v1.5 and PICMG 3.0) List of Supported Commands (IPMI v1.5 and PICMG 3.0) B Table 108. IPMI 1.5 Supported Commands (Sheet 1 of 3) IPM Device Global Commands Command NetFn* CMD IPMI 1.5 Spec Func Get Device ID App 01h 17.1 Cold Reset App 02h 17.2 Get Self Test Results App 04h 17.4 Broadcast "Get Device ID" App ? 17.9 BMC Watchdog Timer Commands Command NetFn* CMD IPMI 1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 108. IPMI 1.5 Supported Commands (Sheet 2 of 3) Event Commands Command NetFn* CMD IPMI 1.5 Spec Func Set Event Receiver S/E 00h 23.1 Get Event Receiver S/E 01h 23.2 Platform Event (Event Message) S/E 02h 23.3 PEF and Alerting Commands Command NetFn* CMD IPMI 1.5 Spec Func Get PEF Capabilities S/E 10h 24.1 Arm PEF Postpone Timer S/E 11h 24.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 108. IPMI 1.5 Supported Commands (Sheet 3 of 3) SDR Device Commands Command Run Initialization Agent NetFn* Storage CMD 2Ch IPMI 1.5 Spec Func 27.21 SEL Device Commands Command NetFn* CMD IPMI 1.5 Spec Func Get SEL Info Storage 40h 25.2 Get SEL Allocation Info Storage 41h 25.3 Reserve SEL Storage 42h 25.4 Get SEL Entry Storage 43h 25.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 109. PICMG 3.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 110. IPMI 2.0 Supported Commands (Continued) BMC Device and Messaging Commands Command NetFn* CMD IPMI2.0 Spec Func Set User Name App 45h 22.28 Get User Name Command App 46h 22.29 Set User Password Command App 47h 22.30 Activate Payload App 48h 24.1 Deactivate Payload App 49h 24.2 Get Payload Activation Status App 4Ah 24.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Material Declaration Data Sheets Material Declaration Data Sheets C The following pages provide the Material Declaration Data Sheets for the following: • Intel NetStructure® MPCBL0001 Single Board Compute - MPCBL0001N04Q • Intel NetStructure® MPCBL0001 Single Board Compute - MPCBL0001F04Q 194 Technical Product Specification Order #273817
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Material Declaration Data Sheets Material Declaration Data Sheet Intel NetStructure® MPCBL0001 Single Board Compute MPCBL0001N04Q Pb Free Product: Yes Product Weight (grams): 2281.9 Manufacturer: Intel Corporation Revision Date: 5/31/2006 Restrictions on Hazardous Substances (RoHS) Compliance RoHS Definition * Quantity limit of 0.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Material Declaration Data Sheets If this product contains materials listed in Annex B of the EIA/EICTA/JGPSSI Material Composition Declaration Guide above the threshold level of 1000 ppm, those materials/substances are listed below. Description of Use Location in Product Material Concentration (ppm) Brominated Flame Retardant Flame Retardant Cables and/or Connectors 12400 Nickel Part Finish Components 2570 COMMENTS 1.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Material Declaration Data Sheets Material Declaration Data Sheet Intel NetStructure® MPCBL0001 Single Board Compute MPCBL0001F04Q Pb Free Product: Yes Product Weight (grams): 2281.9 Manufacturer: Intel Corporation Revision Date: 5/25/2006 Restrictions on Hazardous Substances (RoHS) Compliance RoHS Definition * Quantity limit of 0.
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Intel NetStructure® MPCBL0001 High Performance Single Board Computer Material Declaration Data Sheets If this product contains materials listed in Annex B of the EIA/EICTA/JGPSSI Material Composition Declaration Guide above the threshold level of 1000 ppm, those materials/substances are listed below. Description of Use Location in Product Material Concentration (ppm) Brominated Flame Retardant Nickel 12400 Part Finish Components 2570 COMMENTS 1.