Debug Port Design Guide for UP/DP Systems

Overview
10 DPDG for UP/DP Systems Order Number: 313373-001
Electrical lengths are provided in units of flight-time. Conversion of flight time to board
trace lengths is dependent on what layer routing occurs on, and the dielectric constant
of the board materials for a specific design. Rule of thumb numbers can be derived by
using 140-180ps/inch for outer layers of an FR4 product and 180ps/inch for inner
layers.
All JTAG and BPM# signals must be routed using 45-65 ohm +/-10% impedance traces.
The length of any unterminated stub on any of these nets must be less than 200ps
unless otherwise stated. JTAG and BPM# signals may optionally be terminated using
the nominal board impedance. The 51 +/- 5% ohm recommendation in this document
has been proven to work on all board impedances tested to date.
VTAP for single or dual processor systems will be the VTT rail (or system bus IO
voltage) of the processors
In all drawings, signals that are not connected may be assumed to be left floating thus
no termination is required.
All diagrams show the preferred implementation of passing a signal through the ball
and out to a termination. However, because of breakout constraints within the
processor zones a designer could T off the termination prior to the processor ball. In
that case the stub to the processor cannot exceed 200pS in length.
TCK0, system clocks, and all of the observation pins should be routed with high-speed
design rules in mind. In particular:
• An effort should be made to minimize the number of layer transitions and plane
split crossings imposed on each trace (ideally this will be zero). If return paths are
well kept then the number of vias are nearly immaterial. A good rule of thumb
would be to use no more than 3 vias and/or spend extra effort to insure good
return path currents.
• Keep the critical signals referenced to GND whenever possible.
• Include stitching vias near every layer transition. This is important even when
referencing the same voltage on the new layer because the stitching via may
reduce return current loops on the trace.
• Include a bypass capacitor near every layer transition or plane split between the
two referenced planes.
• An effort should be made not to share XDP bypass capacitors with other high-speed
signals.
• For all signals, pull-up termination resistors should be located above a solid power
plane. If a solid power plane does not exist at the required termination location,
add a 0.1uF ceramic capacitor to GND on the pull-up voltage within 0.5 inches of
termination resistor.
2.1.1 Termination Resistors
Termination resistances are given with tolerances whenever appropriate. If given,
tolerances are within +/- of the percentage given.
With few exceptions (noted specifically in their description), termination resistors must
be close to the receiver. The topology at the end of the chain must be terminated in one
of the following ways in all cases except those noted in their specific description.