Debug Port Design Guide for UP/DP Systems

XDP Design Guide
14 DPDG for UP/DP Systems Order Number: 313373-001
Notes:
A - These resistors will either be opens (if the processor has on-die termination) or 51
ohm 5% (if processor has no on-die termination)
B - This routing length is unconstrained.
C - Maximum routing of these signals are 1.5ns and must be length matched to one
another within 50 ps.
D - This routing length must be a maximum of 1.5ns.
E - These traces have no specific routing length requirements.
F - These traces lengths are determined by the driver and driver termination.
G - This trace length must not exceed 200ps -- see the datasheet.
I - This resistance is dependant on the front panel circuit receiver.
Z - Source termination method is defined by the clock driver.
All signals not noted except TDI and TDO are to be left NC.
Figure 3-1. XDP UP Routing Overview
51
5%
Processor
BPM0#
BPM1#
BPM2#
BPM3#
BPM4# (PRDY)
BPM5# (PREQ)
TMS
TCK
TRST#
RESET#
PWRGOOD
eXtended
Debug
Port
VCC_OBS_CD
VCC_OBS_AB
OBSDATA_A3
OBSDATA_A2
OBSDATA_A1
OBSDATA_A0
OBSFN_A1
OBSFN_A0
TMS
TCK0
TRSTn
HOOK0
HOOK4
HOOK5
HOOK6
HOOK7
XDP PRESENT
GND
1K 5%
51
5%
Vtt
51
5%
A
A
A
A
Front Panel Reset
XDP detect circuit
Clock
Generator
ClkOut
ClkOut#
E
C
C
C
C
C
C
D
E
G E
B
B
B
B
E
B
E
E
F
F
E
B
1.5-3.3VDC
I
E
Z
E
B
A
A
B