Debug Port Design Guide for UP/DP Systems

DPDG for UP/DP Systems Order Number: 313373-001 23
XDP Design Guide
Table 3-1. XDP Pinouts
Pin Sig name
Target Sig
Name
I/O Device Pin Sig name
Target Sig
Name
I/O Device
1 GND GND 2 GND GND
3 OBSFN_A0 BPM[5]# I/O processor
2
4OBSFN_C0 OPEN I/O
5 OBSFN_A1 BPM[4]# I/O processor
2
6OBSFN_C1 OPEN I/O
7 GND GND 8 GND GND
9 OBSDATA_A[0] BPM[3]# I/O processor
2
10 OBSDATA_C[0] OPEN I/O
11 OBSDATA_A[1] BPM[2]# I/O processor
2
12 OBSDATA_C[1] OPEN I/O
13 GND GND 14 GND GND
15 OBSDATA_A[2] BPM[1]# I/O processor
2
16 OBSDATA_C[2] OPEN I/O
17 OBSDATA_A[3] BPM[0]# I/O processor
2
18 OBSDATA_C[3] OPEN I/O
19 GND GND 20 GND GND
21 OBSFN_B0 BPM[5]# I/O processor
2
22 OBSFN_D0 OPEN I/O
23 OBSFN_B1 BPM[4]# I/O processor
2
24 OBSFN_D1 OPEN I/O
25 GND GND 26 GND GND
27 OBSDATA_B[0] BPM[3]# I/O processor
2
28 OBSDATA_D[0] OPEN I/O
29 OBSDATA_B[1] BPM[2]# I/O processor
2
30 OBSDATA_D[1] OPEN I/O
31 GND GND 32 GND GND
33 OBSDATA_B[2] BPM[1]# I/O processor
2
34 OBSDATA_D[2] OPEN I/O
35 OBSDATA_B[3] BPM[0]# I/O processor
2
36 OBSDATA_D[3] OPEN I/O
37 GND GND 38 GND GND
39 HOOK0 PWRGOOD I 40 HOOK4 BCLK[0] I System
41 HOOK1 OPEN 42 HOOK5 BCLK[1] I System
43 VCC_OBS_AB Vtt I System 44 VCC_OBS_CD Vtt I System
45 HOOK2 OPEN 46 HOOK6 RESET# I System
47 HOOK3 OPEN 48 HOOK7 front panel
reset
1
OSystem
49 GND GND 50 GND GND
51 SDA 2 I/O I2C* 52 TDO TDO I processor
2
53 SCL 2 I/O I2C* 54 TRSTn TRSTn O processor
2
55 RESERVED RESERVED 56 TDI TDI O processor
2
57 TCK0 TCK O processor
2
58 TMS TMS O processor
2
59 GND GND 60 XDP Present O 3
Notes:
1. See specific descriptions of these signals for additional information
2. To the appropriate processor(s) -- see the description of each signal for more information.
3. Optional use.