Debug Port Design Guide for UP/DP Systems

ITP700Flex Design Guide
34 DPDG for UP/DP Systems Order Number: 313373-001
Notes:
A - These resistors will either be opens (if the processor has on-die termination) or 51
ohm 5% (if processor has no on-die termination).
B - These routings have no routing length constraint.
C - All of these routings must be a maximum of 1.5ns. They also must be length
matched to within 50ps of one another.
D - These traces must be a maximum of 1.5ns.
E - These traces have no specific routing requirements.
F - These traces lengths are determined the length of the signals from the clock
generator to the processor plus the length of the Obs_Data signals.
G - Tie VTT and VTAP together and place the ceramic buffering capacitor within 0.1
inches of the ITP700Flex.
H - Maximum trace routing of 200ps.
I - This resistance and termination voltage is dependent on the front panel circuit
receiver.
Z - Source termination method is defined by the clock driver.
All signals not noted except TDI and TDO are to be left NC.
Figure 5-1. ITP700Flex Routing Overview
27
1%
Processor
BPM0
BPM1
BPM2
BPM3
BPM4(PRDY)
BPM5(PREQ)
TDI
TDO
TMS
TCK
TRST#
RESET#
ITP700Flex
Debug Port
VTAP
VTT
OBSDATA_A3
OBSDATA_A2
OBSDATA_A1
OBSDATA_A0
OBSFN_A1
OBSFN_A0
TDI
TDO
TMS
TCK
TRST#
FBO
HOOK4
HOOK5
HOOK6
HOOK7
GND
150 5%
39
1%
Vtt
500-680
5%
A
A
A
A
Front Panel Reset
Clock
Generator
ClkOut
ClkOut#
E
C
C
C
C
C
C
D
E
H
E
B
B
B
B
E
H
E
F
F
H
E
E
150
5%
51
5%
H
H
c
1.5-3.3VDC
I
E
Z
A
B
0.1uF
G
B
A