Debug Port Design Guide for UP/DP Systems

DPDG for UP/DP Systems Order Number: 313373-001 9
Overview
2 Overview
The debug port is a connection into a target system environment that provides access
to JTAG, run control, and in some cases system control resources. Debug ports come
in three styles; XDP, XDP-Sinned ITP700Flex.
The eXtended Debug Port (XDP) is a 60-pin, small form factor connector, and is the
recommended implementation as it provides for additional silicon / system debug
resources compared to other debug port implementations and provides for expansion
for future capabilities. Using XDP could save valuable time if debug by Intel is required.
Most commercially available run control tools only interface to the XDP port.
Additionally XDP extends JTAG by permitting implementation of two separate clock
domain scan chains. The goal of dividing the system scan chains into two domains is to
increase the operating frequency of the processor scan chain by moving the typically
slower chipset JTAG agents to a completely separate clock domain. This was not
possible using ITP700Flex or the previous generation of run control tool hardware. XDP
also provides assistance in management and debug of power, reset and clocking.
For design guidelines with XDP, see the guidelines in this chapter and also Section 3,
“XDP Design Guide” on page 13
XDP-SSA (Second Side Attach) is a 31-pin alternative to XDP for those customers
needing to place the debug port on the non-component side of the board. XDP’s fine
pitch has historically not fared well in a hand soldered environment. As there are fewer
pins, XDP-SSA has less capabilities than XDP, primarily in that it only has a single
Observability Port.
Use of the XDP-SSA connector in board designs will require the use of an XDP to XDP-
SSA adapter during system debug. Contact the debug tool vendor for information on
this adapter.
For design guidelines with XDP-SSA, see the guidelines in this chapter and also Section
4, “XDP-SSA Design Guide” on page 27
ITP700Flex is a slightly smaller form factor, 28-pin interface with a significantly smaller
connection keep-out volume. ITP700Flex only allows for JTAG, run control and small
amounts of system control resources. It does not allow for SMBUS support. The
maximum speed of an ITP700Flex implementation is also limited compared to the XDP
implementation.
For design guidelines for ITP700Flex, see Section 5, “ITP700Flex Design Guide” on
page 33.
2.1 General Guidelines
These guidelines apply to XDP designs, XDP-SSA and ITP700Flex designs.
For some signals, the existence of on-die termination (ODT) within the processor or
chipset will remove parts from the platform design. The processor or chipset specific
datasheet will clarify if ODT exists on signals from this design guideline.