Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

ManualsBrandsIntel ManualsOtherIntel Pentium 4 Processor 2.80 GHz, 512K Cache, 533 MHz FSB

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Vol. 1 4-23

DATA TYPES

operand address field of the exception pointer will point to the NaN, and the NaN will

contain the index number of the array element.

Quiet NaNs are often used to speed up debugging. In its early testing phase, a

program often contains multiple errors. An exception handler can be written to save

diagnostic information in memory whenever it was invoked. After storing the diag-

nostic data, it can supply a quiet NaN as the result of the erroneous instruction, and

that NaN can point to its associated diagnostic area in memory. The program will

then continue, creating a different NaN for each error. When the program ends, the

NaN results can be used to access the diagnostic data saved at the time the errors

occurred. Many errors can thus be diagnosed and corrected in one test run.

In embedded applications that use computed results in further computations, an

undetected QNaN can invalidate all subsequent results. Such applications should

therefore periodically check for QNaNs and provide a recovery mechanism to be used

if a QNaN result is detected.

4.8.3.7 QNaN Floating-Point Indefinite

For the floating-point data type encodings (single-precision, double-precision, and

double-extended-precision), one unique encoding (a QNaN) is reserved for repre-

senting the special value QNaN floating-point indefinite. The x87 FPU and the

SSE/SSE2/SSE3 extensions return these indefinite values as responses to some

masked floating-point exceptions. Table 4-3 shows the encoding used for the QNaN

floating-point indefinite.

4.8.4 Rounding

When performing floating-point operations, the processor produces an infinitely

precise floating-point result in the destination format (single-precision, double-preci-

sion, or double extended-precision floating-point) whenever possible. However,

because only a subset of the numbers in the real number continuum can be repre-

sented in IEEE Standard 754 floating-point formats, it is often the case that an infi-

nitely precise result cannot be encoded exactly in the format of the destination

operand.

For example, the following value (a) has a 24-bit fraction. The least-significant bit of

this fraction (the underlined bit) cannot be encoded exactly in the single-precision

format (which has only a 23-bit fraction):

(a) 1.0001 0000 1000 0011 1001 0111

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To round this result (a), the processor first selects two representable fractions b and

c that most closely bracket a in value (b < a < c).

(b) 1.0001 0000 1000 0011 1001 011E

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