Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 4-25
DATA TYPES
The MXCSR register (bits 13 and 14)
Although these two RC fields perform the same function, they control rounding for
different execution environments within the processor. The RC field in the x87 FPU
control register controls rounding for computations performed with the x87 FPU
instructions; the RC field in the MXCSR register controls rounding for SIMD floating-
point computations performed with the SSE/SSE2 instructions.
4.8.4.2 Truncation with SSE and SSE2 Conversion Instructions
The following SSE/SSE2 instructions automatically truncate the results of conver-
sions from floating-point values to integers when the result it inexact: CVTTPD2DQ,
CVTTPS2DQ, CVTTPD2PI, CVTTPS2PI, CVTTSD2SI, CVTTSS2SI. Here, truncation
means the round toward zero mode described in Table 4-8.
4.9 OVERVIEW OF FLOATING-POINT EXCEPTIONS
The following section provides an overview of floating-point exceptions and their
handling in the IA-32 architecture. For information specific to the x87 FPU and to the
SSE/SSE2/SSE3 extensions, refer to the following sections:
Section 8.4, “x87 FPU Floating-Point Exception Handling”
Section 11.5, “SSE, SSE2, and SSE3 Exceptions”
When operating on floating-point operands, the IA-32 architecture recognizes and
detects six classes of exception conditions:
Invalid operation (#I)
Divide-by-zero (#Z)
Denormalized operand (#D)
Numeric overflow (#O)
Numeric underflow (#U)
Inexact result (precision) (#P)
The nomenclature of “#” symbol followed by one or two letters (for example, #P) is
used in this manual to indicate exception conditions. It is merely a short-hand form
and is not related to assembler mnemonics.
NOTE
All of the exceptions listed above except the denormal-operand
exception (#D) are defined in IEEE Standard 754.
The invalid-operation, divide-by-zero and denormal-operand exceptions are pre-
computation exceptions (that is, they are detected before any arithmetic operation