Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

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DATA TYPES
occurs). The numeric-underflow, numeric-overflow and precision exceptions are
post-computation exceptions.
Each of the six exception classes has a corresponding flag bit (IE, ZE, OE, UE, DE, or
PE) and mask bit (IM, ZM, OM, UM, DM, or PM). When one or more floating-point
exception conditions are detected, the processor sets the appropriate flag bits, then
takes one of two possible courses of action, depending on the settings of the corre-
sponding mask bits:
• Mask bit set. Handles the exception automatically, producing a predefined (and
often times usable) result, while allowing program execution to continue undis-
turbed.
• Mask bit clear. Invokes a software exception handler to handle the exception.
The masked (default) responses to exceptions have been chosen to deliver a reason-
able result for each exception condition and are generally satisfactory for most
floating-point applications. By masking or unmasking specific floating-point excep-
tions, programmers can delegate responsibility for most exceptions to the processor
and reserve the most severe exception conditions for software exception handlers.
Because the exception flags are “sticky,” they provide a cumulative record of the
exceptions that have occurred since they were last cleared. A programmer can thus
mask all exceptions, run a calculation, and then inspect the exception flags to see if
any exceptions were detected during the calculation.
In the IA-32 architecture, floating-point exception flag and mask bits are imple-
mented in two different locations:
• x87 FPU status word and control word. The flag bits are located at bits 0 through
5 of the x87 FPU status word and the mask bits are located at bits 0 through 5 of
the x87 FPU control word (see Figures 8-4 and 8-6).
• MXCSR register. The flag bits are located at bits 0 through 5 of the MXCSR
register and the mask bits are located at bits 7 through 12 of the register (see
Figure 10-3).
Although these two sets of flag and mask bits perform the same function, they
report on and control exceptions for different execution environments within the
processor. The flag and mask bits in the x87 FPU status and control words control
exception reporting and masking for computations performed with the x87 FPU
instructions; the companion bits in the MXCSR register control exception reporting
and masking for SIMD floating-point computations performed with the
SSE/SSE2/SSE3 instructions.
Note that when exceptions are masked, the processor may detect multiple excep-
tions in a single instruction, because it continues executing the instruction after
performing its masked response. For example, the processor can detect a denormal-
ized operand, perform its masked response to this exception, and then detect
numeric underflow.
See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules for
exception precedence when more than one floating-point exception condition is
detected for an instruction.