Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 4-31
DATA TYPES
exception occurs frequently and indicates that some (normally acceptable) accuracy
will be lost due to rounding. The exception is supported for applications that need to
perform exact arithmetic only. Because the rounded result is generally satisfactory
for most applications, this exception is commonly masked.
If the inexact-result exception is masked when an inexact-result condition occurs and
a numeric overflow or underflow condition has not occurred, the processor sets the
PE flag and stores the rounded result in the destination operand. The current
rounding mode determines the method used to round the result. See Section 4.8.4,
“Rounding.”
If the inexact-result exception is not masked when an inexact result occurs and
numeric overflow or underflow has not occurred, the PE flag is set, the rounded result
is stored in the destination operand, and a software exception handler is invoked.
If an inexact result occurs in conjunction with numeric overflow or underflow, one of
the following operations is carried out:
• If an inexact result occurs along with masked overflow or underflow, the OE flag
or UE flag and the PE flag are set and the result is stored as described for the
overflow or underflow exceptions; see Section 4.9.1.4, “Numeric Overflow
Exception (#O),” or Section 4.9.1.5, “Numeric Underflow Exception (#U).” If the
inexact result exception is unmasked, the processor also invokes a software
exception handler.
• If an inexact result occurs along with unmasked overflow or underflow and the
destination operand is a register, the OE or UE flag and the PE flag are set, the
result is stored as described for the overflow or underflow exceptions, and a
software exception handler is invoked.
If an unmasked numeric overflow or underflow exception occurs and the destination
operand is a memory location (which can happen only for a floating-point store), the
inexact-result condition is not reported and the C1 flag is cleared.
See the following sections for information regarding the inexact-result exception
when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions:
• x87 FPU; Section 8.5.6, “Inexact-Result (Precision) Exception (#P)”
• SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception
(#Z)”
4.9.2 Floating-Point Exception Priority
The processor handles exceptions according to a predetermined precedence. When
an instruction generates two or more exception conditions, the exception precedence
sometimes results in the higher-priority exception being handled and the lower-
priority exceptions being ignored. For example, dividing an SNaN by zero can poten-
tially signal an invalid-operation exception (due to the SNaN operand) and a divide-
by-zero exception. Here, if both exceptions are masked, the processor handles the
higher-priority exception only (the invalid-operation exception), returning a QNaN to