Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

5-10 Vol. 1
INSTRUCTION SET SUMMARY
5.1.13 Miscellaneous Instructions
The miscellaneous instructions provide such functions as loading an effective address,
executing a “no-operation,” and retrieving processor identification information.
LEA Load effective address
NOP No operation
UD2 Undefined instruction
XLAT/XLATB Table lookup translation
CPUID Processor Identification
5.2 X87 FPU INSTRUCTIONS
The x87 FPU instructions are executed by the processor’s x87 FPU. These instructions
operate on floating-point, integer, and binary-coded decimal (BCD) operands. For
more detail on x87 FPU instructions, see Chapter 8, “Programming with the x87 FPU.”
These instructions are divided into the following subgroups: data transfer, load
constants, and FPU control instructions. The sections that follow introduce each
subgroup.
5.2.1 x87 FPU Data Transfer Instructions
The data transfer instructions move floating-point, integer, and BCD values between
memory and the x87 FPU registers. They also perform conditional move operations
on floating-point operands.
FLD Load floating-point value
FST Store floating-point value
FSTP Store floating-point value and pop
FILD Load integer
FIST Store integer
FISTP
1
Store integer and pop
FBLD Load BCD
FBSTP Store BCD and pop
FXCH Exchange registers
FCMOVE Floating-point conditional move if equal
FCMOVNE Floating-point conditional move if not equal
FCMOVB Floating-point conditional move if below
FCMOVBE Floating-point conditional move if below or equal
1. SSE3 provides an instruction FISTTP for integer conversion.