Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

5-16 Vol. 1
INSTRUCTION SET SUMMARY
5.4.5 MMX Logical Instructions
The logical instructions perform AND, AND NOT, OR, and XOR operations on quad-
word operands.
PAND Bitwise logical AND
PANDN Bitwise logical AND NOT
POR Bitwise logical OR
PXOR Bitwise logical exclusive OR
5.4.6 MMX Shift and Rotate Instructions
The shift and rotate instructions shift and rotate packed bytes, words, or double-
words, or quadwords in 64-bit operands.
PSLLW Shift packed words left logical
PSLLD Shift packed doublewords left logical
PSLLQ Shift packed quadword left logical
PSRLW Shift packed words right logical
PSRLD Shift packed doublewords right logical
PSRLQ Shift packed quadword right logical
PSRAW Shift packed words right arithmetic
PSRAD Shift packed doublewords right arithmetic
5.4.7 MMX State Management Instructions
The EMMS instruction clears the MMX state from the MMX registers.
EMMS Empty MMX state
5.5 SSE INSTRUCTIONS
SSE instructions represent an extension of the SIMD execution model introduced
with the MMX technology. For more detail on these instructions, see Chapter 10,
“Programming with Streaming SIMD Extensions (SSE).”
SSE instructions can only be executed on Intel 64 and IA-32 processors that support
SSE extensions. Support for these instructions can be detected with the CPUID
instruction. See the description of the CPUID instruction in Chapter 3, “Instruction
Set Reference, A-M,” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A.