Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

5-20 Vol. 1
INSTRUCTION SET SUMMARY
5.5.2 SSE MXCSR State Management Instructions
MXCSR state management instructions allow saving and restoring the state of the
MXCSR control and status register.
LDMXCSR Load MXCSR register
STMXCSR Save MXCSR register state
5.5.3 SSE 64-Bit SIMD Integer Instructions
These SSE 64-bit SIMD integer instructions perform additional operations on packed
bytes, words, or doublewords contained in MMX registers. They represent enhance-
ments to the MMX instruction set described in Section 5.4, “MMX™ Instructions.”
PAVGB Compute a verage of packed unsigned byte integers
PAVGW Compute a verage of packed unsigned word integers
PEXTRW Extract word
PINSRW Insert word
PMAXUB Maximum of packed unsigned byte integers
PMAXSW Maximum of packed signed word integers
PMINUB Minimum of packed unsigned byte integers
PMINSW Minimum of packed signed word integers
PMOVMSKB Move byte mask
PMULHUW Multiply packed unsigned integers and store high result
PSADBW Compute sum of absolute differences
PSHUFW Shuffle packed integer word in MMX register
5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering
Instructions
The cacheability control instructions provide control over the caching of non-
temporal data when storing data from the MMX and XMM registers to memory. The
PREFETCHh allows data to be prefetched to a selected cache level. The SFENCE
instruction controls instruction ordering on store operations.
MASKMOVQ Non-temporal store of selected bytes from an MMX register into
memory
MOVNTQ Non-temporal store of quadword from an MMX register into
memory
MOVNTPS Non-temporal store of four packed single-precision floating-
point values from an XMM register into memory