Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 5-27
INSTRUCTION SET SUMMARY
element of the second operand from the first element of the
second operand; and the fourth by subtracting the fourth
element of the second operand from the third element of the
second operand.
HADDPD Performs a double-precision addition on contiguous data
elements. The first data element of the result is obtained by
adding the first and second elements of the first operand; the
second element by adding the first and second elements of the
second operand.
HSUBPD Performs a double-precision subtraction on contiguous data
elements. The first data element of the result is obtained by
subtracting the second element of the first operand from the
first element of the first operand; the second element by
subtracting the second element of the second operand from the
first element of the second operand.
5.7.5 SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE
Instructions
MOVSHDUP Loads/moves 128 bits; duplicating the second and fourth 32-bit
data elements
MOVSLDUP Loads/moves 128 bits; duplicating the first and third 32-bit data
elements
MOVDDUP Loads/moves 64 bits (bits[63:0] if the source is a register) and
returns the same 64 bits in both the lower and upper halves of
the 128-bit result register; duplicates the 64 bits from the
source
5.7.6 SSE3 Agent Synchronization Instructions
MONITOR Sets up an address range used to monitor write-back stores
MWAIT Enables a logical processor to enter into an optimized state while
waiting for a write-back store to the address range set up by the
MONITOR instruction