Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 xv
CONTENTS
PAGE
APPENDIX D
GUIDELINES FOR WRITING X87 FPU
EXCEPTION HANDLERS
D.1 MS-DOS COMPATIBILITY SUB-MODE FOR HANDLING X87 FPU EXCEPTIONS. . . . . . . . . . . D-2
D.2 IMPLEMENTATION OF THE MS-DOS COMPATIBILITY SUB-MODE IN THE
INTEL486, PENTIUM, AND P6 PROCESSOR FAMILY, AND PENTIUM 4 PROCESSORS . . . . D-3
D.2.1 MS-DOS Compatibility Sub-mode in the Intel486 and Pentium Processors. . . . . . . . . . . D-3
D.2.1.1 Basic Rules: When FERR# Is Generated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4
D.2.1.2 Recommended External Hardware to Support the MS-DOS
Compatibility Sub-mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5
D.2.1.3 No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window . . . . . . . . . . . . D-8
D.2.2 MS-DOS Compatibility Sub-mode in the P6 Family
and Pentium 4 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-10
D.3 RECOMMENDED PROTOCOL FOR MS-DOS* COMPATIBILITY HANDLERS . . . . . . . . . . . . . . D-11
D.3.1 Floating-Point Exceptions and Their Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-12
D.3.2 Two Options for Handling Numeric Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-12
D.3.2.1 Automatic Exception Handling: Using Masked Exceptions . . . . . . . . . . . . . . . . . . . . . .D-12
D.3.2.2 Software Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-14
D.3.3 Synchronization Required for Use of x87 FPU Exception Handlers . . . . . . . . . . . . . . . .D-15
D.3.3.1 Exception Synchronization: What, Why and When . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-16
D.3.3.2 Exception Synchronization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-17
D.3.3.3 Proper Exception Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-17
D.3.4 x87 FPU Exception Handling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-18
D.3.5 Need for Storing State of IGNNE# Circuit If Using x87 FPU and SMM . . . . . . . . . . . . . .D-22
D.3.6 Considerations When x87 FPU Shared Between Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . .D-23
D.3.6.1 Speculatively Deferring x87 FPU Saves, General Overview . . . . . . . . . . . . . . . . . . . .D-24
D.3.6.2 Tracking x87 FPU Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-25
D.3.6.3 Interaction of x87 FPU State Saves and Floating-Point Exception
Association . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-25
D.3.6.4 Interrupt Routing From the Kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-28
D.3.6.5 Special Considerations for Operating Systems that Support Streaming
SIMD Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-28
D.4 DIFFERENCES FOR HANDLERS USING NATIVE MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-29
D.4.1 Origin with the Intel 286 and Intel 287, and Intel386 and Intel 387 Processors . . . .D-29
D.4.2 Changes with Intel486, Pentium and Pentium Pro Processors with
CR0.NE[bit 5] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-30
D.4.3 Considerations When x87 FPU Shared Between Tasks Using Native Mode. . . . . . . . .D-30
APPENDIX E
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
E.1 TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.2 SOFTWARE EXCEPTION HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.3 EXCEPTION SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
E.4 SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754 . . . . . . . . . . . . . . . . . . E-4
E.4.1 Floating-Point Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4
E.4.2 SSE/SSE2/SSE3 Response To Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6
E.4.2.1 Numeric Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7