Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

5-30 Vol. 1
INSTRUCTION SET SUMMARY
5.8.6 Packed Sign
PSIGNB/W/D Negates each signed integer element of the destination operand
if the sign of the corresponding data element in the source
operand is less than zero.
5.8.7 Packed Align Right
PALIGNR Source operand is appended after the destination operand
forming an intermediate value of twice the width of an operand.
The result is extracted from the intermediate value into the
destination operand by selecting the 128 bit or 64 bit value that
are right-aligned to the byte offset specified by the immediate
value.
5.9 SYSTEM INSTRUCTIONS
The following system instructions are used to control those functions of the processor
that are provided to support for operating systems and executives.
LGDT Load global descriptor table (GDT) register
SGDT Store global descriptor table (GDT) register
LLDT Load local descriptor table (LDT) register
SLDT Store local descriptor table (LDT) register
LTR Load task register
STR Store task register
LIDT Load interrupt descriptor table (IDT) register
SIDT Store interrupt descriptor table (IDT) register
MOV Load and store control registers
LMSW Load machine status word
SMSW Store machine status word
CLTS Clear the task-switched flag
ARPL Adjust requested privilege level
LAR Load access rights
LSL Load segment limit
VERR Verify segment for reading
VERW Verify segment for writing
MOV Load and store debug registers
INVD Invalidate cache, no writeback
WBINVD Invalidate cache, with writeback
INVLPG Invalidate TLB Entry