Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 6-13
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6.4 INTERRUPTS AND EXCEPTIONS
The processor provides two mechanisms for interrupting program execution, inter-
rupts and exceptions:
• An interrupt is an asynchronous event that is typically triggered by an I/O
device.
• An exception is a synchronous event that is generated when the processor
detects one or more predefined conditions while executing an instruction. The
IA-32 architecture specifies three classes of exceptions: faults, traps, and aborts.
The processor responds to interrupts and exceptions in essentially the same way.
When an interrupt or exception is signaled, the processor halts execution of the
current program or task and switches to a handler procedure that has been written
specifically to handle the interrupt or exception condition. The processor accesses
the handler procedure through an entry in the interrupt descriptor table (IDT). When
the handler has completed handling the interrupt or exception, program control is
returned to the interrupted program or task.
The operating system, executive, and/or device drivers normally handle interrupts
and exceptions independently from application programs or tasks. Application
programs can, however, access the interrupt and exception handlers incorporated in
an operating system or executive through assembly-language calls. The remainder
of this section gives a brief overview of the processor’s interrupt and exception
handling mechanism. See Chapter 5, “Interrupt and Exception Handling,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for a
description of this mechanism.
The IA-32 Architecture defines 18 predefined interrupts and exceptions and 224 user
defined interrupts, which are associated with entries in the IDT. Each interrupt and
exception in the IDT is identified with a number, called a vector. Table 6-1 lists the
interrupts and exceptions with entries in the IDT and their respective vector
numbers. Vectors 0 through 8, 10 through 14, and 16 through 19 are the predefined
interrupts and exceptions, and vectors 32 through 255 are the user-defined inter-
rupts, called maskable interrupts.
Note that the processor defines several additional interrupts that do not point to
entries in the IDT; the most notable of these interrupts is the SMI interrupt. See
Chapter 5, “Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 3B, for more information about the
interrupts and exceptions.
When the processor detects an interrupt or exception, it does one of the following
things:
• Executes an implicit call to a handler procedure.
• Executes an implicit call to a handler task.