Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

6-14 Vol. 1
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6.4.1 Call and Return Operation for Interrupt or Exception
Handling Procedures
A call to an interrupt or exception handler procedure is similar to a procedure call to
another protection level (see Section 6.3.6, “CALL and RET Operation Between Privi-
lege Levels”). Here, the interrupt vector references one of two kinds of gates: an
interrupt gate or a trap gate. Interrupt and trap gates are similar to call gates in
that they provide the following information:
• Access rights information
• The segment selector for the code segment that contains the handler procedure
• An offset into the code segment to the first instruction of the handler procedure
The difference between an interrupt gate and a trap gate is as follows. If an interrupt
or exception handler is called through an interrupt gate, the processor clears the
interrupt enable (IF) flag in the EFLAGS register to prevent subsequent interrupts
from interfering with the execution of the handler. When a handler is called through
a trap gate, the state of the IF flag is not changed.
Table 6-1. Exceptions and Interrupts
Vector
No. Mnemonic Description Source
0 #DE Divide Error DIV and IDIV instructions.
1 #DB Debug Any code or data reference.
2 NMI Interrupt Non-maskable external interrupt.
3 #BP Breakpoint INT 3 instruction.
4 #OF Overflow INTO instruction.
5 #BR BOUND Range Exceeded BOUND instruction.
6 #UD Invalid Opcode (UnDefined
Opcode)
UD2 instruction or reserved opcode.
1
7 #NM Device Not Available (No Math
Coprocessor)
Floating-point or WAIT/FWAIT
instruction.
8 #DF Double Fault Any instruction that can generate an
exception, an NMI, or an INTR.
9 #MF CoProcessor Segment Overrun
(reserved)
Floating-point instruction.
2
10 #TS Invalid TSS Task switch or TSS access.
11 #NP Segment Not Present Loading segment registers or accessing
system segments.
12 #SS Stack Segment Fault Stack operations and SS register loads.