Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 6-15
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
If the code segment for the handler procedure has the same privilege level as the
currently executing program or task, the handler procedure uses the current stack; if
the handler executes at a more privileged level, the processor switches to the stack
for the handler’s privilege level.
If no stack switch occurs, the processor does the following when calling an interrupt
or exception handler (see Figure 6-5):
1. Pushes the current contents of the EFLAGS, CS, and EIP registers (in that order)
on the stack.
2. Pushes an error code (if appropriate) on the stack.
3. Loads the segment selector for the new code segment and the new instruction
pointer (from the interrupt gate or trap gate) into the CS and EIP registers,
respectively.
4. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.
5. Begins execution of the handler procedure.
13 #GP General Protection Any memory reference and other
protection checks.
14 #PF Page Fault Any memory reference.
15 Reserved
16 #MF Floating-Point Error (Math
Fault)
Floating-point or WAIT/FWAIT
instruction.
17 #AC Alignment Check Any data reference in memory.
3
18 #MC Machine Check Error codes (if any) and source are
model dependent.
4
19 #XF SIMD Floating-Point Exception SIMD Floating-Point Instruction
5
20-31 Reserved
32-255 Maskable Interrupts External interrupt from INTR pin or INT
n instruction.
NOTES:
1. The UD2 instruction was introduced in the Pentium Pro processor.
2. IA-32 processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family proces-
sors.
5. This exception was introduced in the Pentium III processor.
Table 6-1. Exceptions and Interrupts (Contd.)
Vector
No. Mnemonic Description Source