Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

7-6 Vol. 1
PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
The XADD (exchange and add) instruction swaps two operands and then stores the
sum of the two operands in the destination operand. The status flags in the EFLAGS
register indicate the result of the addition. This instruction can be combined with the
LOCK prefix (see “LOCK—Assert LOCK# Signal Prefix” in Chapter 3, “Instruction Set
Reference, A-M,” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A) in a multiprocessing system to allow multiple processors to
execute one DO loop.
The CMPXCHG (compare and exchange) and CMPXCHG8B (compare and exchange 8
bytes) instructions are used to synchronize operations in systems that use multiple
processors. The CMPXCHG instruction requires three operands: a source operand in
a register, another source operand in the EAX register, and a destination operand. If
the values contained in the destination operand and the EAX register are equal, the
destination operand is replaced with the value of the other source operand (the value
not in the EAX register). Otherwise, the original value of the destination operand is
loaded in the EAX register. The status flags in the EFLAGS register reflect the result
that would have been obtained by subtracting the destination operand from the value
in the EAX register.
The CMPXCHG instruction is commonly used for testing and modifying semaphores. It
checks to see if a semaphore is free. If the semaphore is free, it is marked allocated;
otherwise it gets the ID of the current owner. This is all done in one uninterruptible
operation. In a single-processor system, the CMPXCHG instruction eliminates the
need to switch to protection level 0 (to disable interrupts) before executing multiple
instructions to test and modify a semaphore.
For multiple processor systems, CMPXCHG can be combined with the LOCK prefix to
perform the compare and exchange operation atomically. (See “Locked Atomic Oper-
ations” in Chapter 7, “Multiple-Processor Management,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A, for more information on
atomic operations.)
Instruction Mnemonic Status Flag States Condition Description
Signed Conditional Moves
CMOVGE/CMOVNL (SF xor OF) = 0 Greater or equal/not less
CMOVL/CMOVNGE (SF xor OF) = 1 Less/not greater or equal
CMOVLE/CMOVNG ((SF xor OF) or ZF) = 1 Less or equal/not greater
CMOVO OF = 1 Overflow
CMOVNO OF = 0 Not overflow
CMOVS SF = 1 Sign (negative)
CMOVNS SF = 0 Not sign (non-negative)
Table 7-2. Conditional Move Instructions (Contd.)