Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 xix
CONTENTS
PAGE
Figure 13-1. Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3
Figure 13-2. I/O Permission Bit Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-6
Figure D-1. Recommended Circuit for MS-DOS Compatibility x87 FPU
Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
Figure D-2. Behavior of Signals During x87 FPU Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . D-8
Figure D-3. Timing of Receipt of External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-9
Figure D-4. Arithmetic Example Using Infinity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-13
Figure D-5. General Program Flow for DNA Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-26
Figure D-6. Program Flow for a Numeric Exception Dispatch Routine . . . . . . . . . . . . . . . . . . . . . .D-27
Figure E-1. Control Flow for Handling Unmasked Floating-Point Exceptions . . . . . . . . . . . . . . . . . E-6