Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

7-32 Vol. 1
PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
• Processor identification
• NOP and undefined instruction entry
7.3.17.1 Address Computation Instruction
The LEA (load effective address) instruction computes the effective address in
memory (offset within a segment) of a source operand and places it in a general-
purpose register. This instruction can interpret any of the processor’s addressing
modes and can perform any indexing or scaling that may be needed. It is especially
useful for initializing the ESI or EDI registers before the execution of string instruc-
tions or for initializing the EBX register before an XLAT instruction.
7.3.17.2 Table Lookup Instructions
The XLAT and XLATB (table lookup) instructions replace the contents of the AL
register with a byte read from a translation table in memory. The initial value in the
AL register is interpreted as an unsigned index into the translation table. This index
is added to the contents of the EBX register (which contains the base address of the
table) to calculate the address of the table entry. These instructions are used for
applications such as converting character codes from one alphabet into another (for
example, an ASCII code could be used to look up its EBCDIC equivalent in a table).
7.3.17.3 Processor Identification Instruction
The CPUID (processor identification) instruction returns information about the
processor on which the instruction is executed.
7.3.17.4 No-Operation and Undefined Instructions
The NOP (no operation) instruction increments the EIP register to point at the next
instruction, but affects nothing else.
The UD2 (undefined) instruction generates an invalid opcode exception. Intel
reserves the opcode for this instruction for this function. The instruction is provided
to allow software to test an invalid opcode exception handler.