Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

8-2 Vol. 1
PROGRAMMING WITH THE X87 FPU
The x87 FPU executes instructions from the processor’s normal instruction stream.
The state of the x87 FPU is independent from the state of the basic execution envi-
ronment and from the state of SSE/SSE2/SSE3 extensions.
However, the x87 FPU and Intel MMX technology share state because the MMX regis-
ters are aliased to the x87 FPU data registers. Therefore, when writing code that uses
x87 FPU and MMX instructions, the programmer must explicitly manage the x87 FPU
and MMX state (see Section 9.5, “Compatibility with x87 FPU Architecture”).
8.1.1 x87 FPU in 64-Bit Mode and Compatibility Mode
In compatibility mode and 64-bit mode, x87 FPU instructions function like they do in
protected mode. Memory operands are specified using the ModR/M, SIB encoding
that is described in Section 3.7.5, “Specifying an Offset.”
8.1.2 x87 FPU Data Registers
The x87 FPU data registers (shown in Figure 8-1) consist of eight 80-bit registers.
Values are stored in these registers in the double extended-precision floating-point
format shown in Figure 4-3. When floating-point, integer, or packed BCD integer
values are loaded from memory into any of the x87 FPU data registers, the values are
automatically converted into double extended-precision floating-point format (if they
are not already in that format). When computation results are subsequently trans-
ferred back into memory from any of the x87 FPU registers, the results can be left in
the double extended-precision floating-point format or converted back into a shorter
floating-point format, an integer format, or the packed BCD integer format. (See
Section 8.2, “x87 FPU Data Types,” for a description of the data types operated on by
the x87 FPU.)