Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 8-7
PROGRAMMING WITH THE X87 FPU
are used principally for conditional branching and for storage of information used in
exception handling (see Section 8.1.4, “Branching and Conditional Moves on Condi-
tion Codes”).
As shown in Table 8-1, the C1 condition code flag is used for a variety of functions.
When both the IE and SF flags in the x87 FPU status word are set, indicating a stack
overflow or underflow exception (#IS), the C1 flag distinguishes between overflow
(C1 = 1) and underflow (C1 = 0). When the PE flag in the status word is set, indi-
cating an inexact (rounded) result, the C1 flag is set to 1 if the last rounding by the
instruction was upward. The FXAM instruction sets C1 to the sign of the value being
examined.
The C2 condition code flag is used by the FPREM and FPREM1 instructions to indicate
an incomplete reduction (or partial remainder). When a successful reduction has
been completed, the C0, C3, and C1 condition code flags are set to the three least-
significant bits of the quotient (Q2, Q1, and Q0, respectively). See “FPREM1—Partial
Remainder” in Chapter 3, “Instruction Set Reference, A-M,” of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A, for more information
on how these instructions use the condition code flags.
The FPTAN, FSIN, FCOS, and FSINCOS instructions set the C2 flag to 1 to indicate
that the source operand is beyond the allowable range of ±2
63
and clear the C2 flag
if the source operand is within the allowable range.
Where the state of the condition code flags are listed as undefined in Table 8-1, do
not rely on any specific value in these flags.
8.1.3.3 x87 FPU Floating-Point Exception Flags
The six x87 FPU floating-point exception flags (bits 0 through 5) of the x87 FPU
status word indicate that one or more floating-point exceptions have been detected
since the bits were last cleared. The individual exception flags (IE, DE, ZE, OE, UE,
and PE) are described in detail in Section 8.4, “x87 FPU Floating-Point Exception
Handling.” Each of the exception flags can be masked by an exception mask bit in the
x87 FPU control word (see Section 8.1.5, “x87 FPU Control Word”). The exception
summary status flag (ES, bit 7) is set when any of the unmasked exception flags are
set. When the ES flag is set, the x87 FPU exception handler is invoked, using one of
the techniques described in Section 8.7, “Handling x87 FPU Exceptions in Software.”
(Note that if an exception flag is masked, the x87 FPU will still set the appropriate
flag if the associated exception occurs, but it will not set the ES flag.)
The exception flags are “sticky” bits (once set, they remain set until explicitly
cleared). They can be cleared by executing the FCLEX/FNCLEX (clear exceptions)
instructions, by reinitializing the x87 FPU with the FINIT/FNINIT or FSAVE/FNSAVE
instructions, or by overwriting the flags with an FRSTOR or FLDENV instruction.
The B-bit (bit 15) is included for 8087 compatibility only. It reflects the contents of
the ES flag.