Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

8-10 Vol. 1
PROGRAMMING WITH THE X87 FPU
The new mechanism is available beginning with the P6 family processors. Using this
mechanism, the new floating-point compare and set EFLAGS instructions (FCOMI,
FCOMIP, FUCOMI, and FUCOMIP) compare two floating-point values and set the ZF,
PF, and CF flags in the EFLAGS register directly. A single instruction thus replaces the
three instructions required by the old mechanism.
Note also that the FCMOVcc instructions (also new in the P6 family processors) allow
conditional moves of floating-point values (values in the x87 FPU data registers)
based on the setting of the status flags (ZF, PF, and CF) in the EFLAGS register. These
instructions eliminate the need for an IF statement to perform conditional moves of
floating-point values.
8.1.5 x87 FPU Control Word
The 16-bit x87 FPU control word (see Figure 8-6) controls the precision of the x87
FPU and rounding method used. It also contains the x87 FPU floating-point exception
mask bits. The control word is cached in the x87 FPU control register. The contents of
this register can be loaded with the FLDCW instruction and stored in memory with the
FSTCW/FNSTCW instructions.
Figure 8-5. Moving the Condition Codes to the EFLAGS Register
0
Condition
Code
Status
Flag
C0
C1
C2
C3
CF
(none)
PF
ZF
C
F
1
P
F
Z
F
731
EFLAGS Register
0
C
2
C
1
C
3
AX Register
0
C
15
0
C
2
C
1
C
3
x87 FPU Status Word
0
C
15
FSTSW AX Instruction
SAHF Instruction