Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

8-12 Vol. 1
PROGRAMMING WITH THE X87 FPU
The double precision and single precision settings reduce the size of the significand to
53 bits and 24 bits, respectively. These settings are provided to support IEEE Stan-
dard 754 and to provide compatibility with the specifications of certain existing
programming languages. Using these settings nullifies the advantages of the double
extended-precision floating-point format's 64-bit significand length. When reduced
precision is specified, the rounding of the significand value clears the unused bits on
the right to zeros.
The precision-control bits only affect the results of the following floating-point
instructions: FADD, FADDP, FIADD, FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR,
FMUL, FMULP, FIMUL, FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR, and FSQRT.
8.1.5.3 Rounding Control Field
The rounding-control (RC) field of the x87 FPU control register (bits 10 and 11)
controls how the results of x87 FPU floating-point instructions are rounded. See
Section 4.8.4, “Rounding,” for a discussion of rounding of floating-point values; See
Section 4.8.4.1, “Rounding Control (RC) Fields”, for the encodings of the RC field.
8.1.6 Infinity Control Flag
The infinity control flag (bit 12 of the x87 FPU control word) is provided for compati-
bility with the Intel 287 Math Coprocessor; it is not meaningful for later version x87
FPU coprocessors or IA-32 processors. See Section 4.8.3.3, “Signed Infinities,” for
information on how the x87 FPUs handle infinity values.
8.1.7 x87 FPU Tag Word
The 16-bit tag word (see Figure 8-7) indicates the contents of each the 8 registers in
the x87 FPU data-register stack (one 2-bit tag per register). The tag codes indicate
whether a register contains a valid number, zero, or a special floating-point number
(NaN, infinity, denormal, or unsupported format), or whether it is empty. The x87
FPU tag word is cached in the x87 FPU in the x87 FPU tag word register. When the x87
FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87
FPU tag word is set to FFFFH, which marks all the x87 FPU data registers as empty.
Table 8-2. Precision Control Field (PC)
Precision PC Field
Single Precision (24 bits) 00B
Reserved 01B
Double Precision (53 bits) 10B
Double Extended Precision (64 bits) 11B