Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

8-14 Vol. 1

PROGRAMMING WITH THE X87 FPU

Note that the value in the x87 FPU data pointer register is always a pointer to a

memory operand, If the last non-control instruction that was executed did not have

a memory operand, the value in the data pointer register is undefined (reserved).

The contents of the x87 FPU instruction and data pointer registers remain unchanged

when any of the control instructions (FINIT/FNINIT, FCLEX/FNCLEX, FLDCW,

FSTCW/FNSTCW, FSTSW/FNSTSW, FSTENV/FNSTENV, FLDENV, FSAVE/FNSAVE,

FRSTOR, and WAIT/FWAIT) are executed.

The pointers stored in the x87 FPU instruction and data pointer registers consist of an

offset (stored in bits 0 through 31) and a segment selector (stored in bits 32

through 47).

These registers can be accessed by the FSTENV/FNSTENV, FLDENV, FINIT/FNINIT,

FSAVE/FNSAVE, FRSTOR, FXSAVE, and FXRSTOR instructions. The FINIT/FNINIT and

FSAVE/FNSAVE instructions clear these registers.

For all the x87 FPUs and NPXs except the 8087, the x87 FPU instruction pointer points

to any prefixes that preceded the instruction. For the 8087, the x87 FPU instruction

pointer points only to the actual opcode.

8.1.9 Last Instruction Opcode

The x87 FPU stores the opcode of the last non-control instruction executed in an

11-bit x87 FPU opcode register. (This information provides state information for

exception handlers.) Only the first and second opcode bytes (after all prefixes) are

stored in the x87 FPU opcode register. Figure 8-8 shows the encoding of these two

bytes. Since the upper 5 bits of the first opcode byte are the same for all floating-

point opcodes (11011B), only the lower 3 bits of this byte are stored in the opcode

8.1.9.1 Fopcode Compatibility Sub-mode

Beginning with the Pentium 4 and Intel Xeon processors, the IA-32 architecture

provides program control over the storing of the last instruction opcode (sometimes

referred to as the fopcode). Here, bit 2 of the IA32_MISC_ENABLE MSR enables (set)

or disables (clear) the fopcode compatibility mode.

If FOP code compatibility mode is enabled, the FOP is defined as it has always been

in previous IA32 implementations (always defined as the FOP of the last non-trans-

parent FP instruction executed before a FSAVE/FSTENV/FXSAVE). If FOP code

compatibility mode is disabled (default), FOP is only valid if the last non-transparent

FP instruction executed before a FSAVE/FSTENV/FXSAVE had an unmasked exception.