Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 8-21
PROGRAMMING WITH THE X87 FPU
Table 8-3. Unsupported Double Extended-Precision Floating-Point Encodings and
Pseudo-Denormals
Class Sign Biased Exponent
Significand
Integer Fraction
Positive
Pseudo-NaNs Quiet
0
.
0
11..11
.
11..11
011..11
.
10..00
Signaling
0
.
0
11..11
.
11..11
0 01..11
.
00..01
Positive Floating
Point
Pseudo-infinity 0 11..11 0 00..00
Unnormals
0
.
0
11..10
.
00..01
011..11
.
00..00
Pseudo-denormals 0
.
0
00..00
.
00..00
111..11
.
00..00
Negative
Floating Point
Pseudo-denormals 1
.
1
00..00
.
00..00
111..11
.
00..00
Unnormals
1
.
1
11..10
.
00..01
011..01
.
00..00
Pseudo-infinity 1 11..11 0 00..00
Negative
Pseudo-NaNs Signaling
1
.
1
11..11
.
11..11
001..11
.
00..01
Quiet
1
.
1
11..11
.
11..11
011..11
.
10..00
← 15 bits →← 63 bits →