Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

8-28 Vol. 1
PROGRAMMING WITH THE X87 FPU
FCOMP instructions, except that they set the status flags (ZF, PF, and CF) in the
EFLAGS register to indicate the results of the comparison (see Table 8-7) instead of
the x87 FPU condition code flags. The FCOMI and FCOMIP instructions allow condition
branch instructions (Jcc) to be executed directly from the results of their comparison.
Software can check if the FCOMI and FCOMIP instructions are supported by checking
the processor’s feature information with the CPUID instruction.
The FUCOMI and FUCOMIP instructions operate the same as the FCOMI and FCOMIP
instructions, except that they do not generate a floating-point invalid-operation
exception if the unordered condition is the result of one or both of the operands being
a QNaN. The FCOMIP and FUCOMIP instructions pop the x87 FPU register stack
following the comparison operation.
The FXAM instruction determines the classification of the floating-point value in the
ST(0) register (that is, whether the value is zero, a denormal number, a normal finite
number, ∞, a NaN, or an unsupported format) or that the register is empty. It sets the
x87 FPU condition code flags to indicate the classification (see “FXAM—Examine” in
Chapter 3, “Instruction Set Reference, A-M,” of the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 2A). It also sets the C1 flag to indicate
the sign of the value.
8.3.6.1 Branching on the x87 FPU Condition Codes
The processor does not offer any control-flow instructions that branch on the setting
of the condition code flags (C0, C2, and C3) in the x87 FPU status word. To branch on
the state of these flags, the x87 FPU status word must first be moved to the AX
register in the integer unit. The FSTSW AX (store status word) instruction can be
used for this purpose. When these flags are in the AX register, the TEST instruction
can be used to control conditional branching as follows:
1. Check for an unordered result. Use the TEST instruction to compare the
contents of the AX register with the constant 0400H (see Table 8-8). This
operation will clear the ZF flag in the EFLAGS register if the condition code flags
indicate an unordered result; otherwise, the ZF flag will be set. The JNZ
instruction can then be used to transfer control (if necessary) to a procedure for
handling unordered operands.
Table 8-7. Setting of EFLAGS Status Flags for Floating-Point Number Comparisons
Comparison Results ZF PF CF
ST0 > ST(i)000
ST0 < ST(i)001
ST0 = ST(i)100
Unordered 1 1 1