Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

8-34 Vol. 1

PROGRAMMING WITH THE X87 FPU

Section D.2.1.3, “No-Wait x87 FPU Instructions Can Get x87 FPU

Interrupt in Window.”

When operating a P6 family, Pentium 4, or Intel Xeon processor in

MS-DOS compatibility mode, non-waiting instructions can not be

interrupted in this way (see Section D.2.2, “MS-DOS Compatibility

Sub-mode in the P6 Family and Pentium 4 Processors”).

8.3.13 Unsupported x87 FPU Instructions

The Intel 8087 instructions FENI and FDISI and the Intel 287 math coprocessor

instruction FSETPM perform no function in the Intel 387 math coprocessor and later

IA-32 processors. If these opcodes are detected in the instruction stream, the x87

FPU performs no specific operation and no internal x87 FPU states are affected.

8.4 X87 FPU FLOATING-POINT EXCEPTION HANDLING

The x87 FPU detects the six classes of exception conditions described in Section 4.9,

“Overview of Floating-Point Exceptions”:

• Invalid operation (#I), with two subclasses:

— Stack overflow or underflow (#IS)

— Invalid arithmetic operation (#IA)

• Denormalized operand (#D)

• Divide-by-zero (#Z)

• Numeric overflow (#O)

• Numeric underflow (#U)

• Inexact result (precision) (#P)

Each of the six exception classes has a corresponding flag bit in the x87 FPU status

word and a mask bit in the x87 FPU control word (see Section 8.1.3, “x87 FPU Status

exception summary (ES) flag in the status word indicates when one or more

unmasked exceptions has been detected. The stack fault (SF) flag (also in the status

word) distinguishes between the two types of invalid-operation exceptions.

The mask bits can be set with FLDCW, FRSTOR, or FXRSTOR; they can be read with

either FSTCW/FNSTCW, FSAVE/FNSAVE, or FXSAVE. The flag bits can be read with

the FSTSW/FNSTSW, FSAVE/FNSAVE, or FXSAVE instruction.

NOTE

Section 4.9.1, “Floating-Point Exception Conditions,” provides a

general overview of how the IA-32 processor detects and handles the