Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 1-3
ABOUT THIS MANUAL
Chapter 4 — Data Types. Describes the data types and addressing modes recog-
nized by the processor; provides an overview of real numbers and floating-point
formats and of floating-point exceptions.
Chapter 5 — Instruction Set Summary. Lists all Intel 64 and IA-32 instructions,
divided into technology groups.
Chapter 6 — Procedure Calls, Interrupts, and Exceptions. Describes the proce-
dure stack and mechanisms provided for making procedure calls and for servicing
interrupts and exceptions.
Chapter 7 — Programming with General-Purpose Instructions. Describes
basic load and store, program control, arithmetic, and string instructions that
operate on basic data types, general-purpose and segment registers; also describes
system instructions that are executed in protected mode.
Chapter 8 — Programming with the x87 FPU. Describes the x87 floating-point
unit (FPU), including floating-point registers and data types; gives an overview of the
floating-point instruction set and describes the processor's floating-point exception
conditions.
Chapter 9 — Programming with Intel
®
MMX™ Technology. Describes Intel
MMX technology, including MMX registers and data types; also provides an overview
of the MMX instruction set.
Chapter 10 — Programming with Streaming SIMD Extensions (SSE).
Describes SSE extensions, including XMM registers, the MXCSR register, and packed
single-precision floating-point data types; provides an overview of the SSE instruc-
tion set and gives guidelines for writing code that accesses the SSE extensions.
Chapter 11 — Programming with Streaming SIMD Extensions 2 (SSE2).
Describes SSE2 extensions, including XMM registers and packed double-precision
floating-point data types; provides an overview of the SSE2 instruction set and gives
guidelines for writing code that accesses SSE2 extensions. This chapter also
describes SIMD floating-point exceptions that can be generated with SSE and SSE2
instructions. It also provides general guidelines for incorporating support for SSE and
SSE2 extensions into operating system and applications code.
Chapter 12 — Programming with SSE3 and Supplemental SSE3. Describes
SSE3 extensions; provides an overview of the SSE3 instruction set, Supplemental
SSE3 and guidelines for writing code that accesses these extensions.
Chapter 13 — Input/Output. Describes the processor’s I/O mechanism, including
I/O port addressing, I/O instructions, and I/O protection mechanisms.
Chapter 14 — Processor Identification and Feature Determination. Describes
how to determine the CPU type and features available in the processor.
Appendix A — EFLAGS Cross-Reference. Summarizes how the IA-32 instructions
affect the flags in the EFLAGS register.
Appendix B — EFLAGS Condition Codes. Summarizes how conditional jump,
move, and ‘byte set on condition code’ instructions use condition code flags (OF, CF,
ZF, SF, and PF) in the EFLAGS register.