Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 8-39
PROGRAMMING WITH THE X87 FPU
Normally, when one or both of the source operands is a QNaN (and neither is an
SNaN or in an unsupported format), an invalid-operand exception is not generated.
An exception to this rule is most of the compare instructions (such as the FCOM and
FCOMI instructions) and the floating-point to integer conversion instructions
(FIST/FISTP and FBSTP). With these instructions, a QNaN source operand will
generate an invalid-operand exception.
8.5.2 Denormal Operand Exception (#D)
The x87 FPU signals the denormal-operand exception under the following conditions:
• If an arithmetic instruction attempts to operate on a denormal operand (see
Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”).
• If an attempt is made to load a denormal single-precision or double-precision
floating-point value into an x87 FPU register. (If the denormal value being loaded
is a double extended-precision floating-point value, the denormal-operand
exception is not reported.)
The flag (DE) for this exception is bit 1 of the x87 FPU status word, and the mask bit
(DM) is bit 1 of the x87 FPU control word.
When a denormal-operand exception occurs and the exception is masked, the x87
FPU sets the DE flag, then proceeds with the instruction. The denormal operand in
single- or double-precision floating-point format is automatically normalized when
converted to the double extended-precision floating-point format. Subsequent oper-
ations will benefit from the additional precision of the internal double extended-preci-
sion floating-point format.
When a denormal-operand exception occurs and the exception is not masked, the DE
flag is set and a software exception handler is invoked (see Section 8.7, “Handling
x87 FPU Exceptions in Software”). The top-of-stack pointer (TOP) and source oper-
ands remain unchanged.
For additional information about the denormal-operation exception, see Section
4.9.1.2, “Denormal Operand Exception (#D).”
FIST/FISTP: Converted value exceeds
representable integer range of the destination
operand, or source value is an SNaN, QNaN, ±∞, or
in an unsupported format.
Store integer indefinite value in the
destination operand.
FXCH: one or both registers are tagged empty. Load empty registers with the QNaN floating-
point indefinite value, then perform the
exchange.
Table 8-10. Invalid Arithmetic Operations and the
Masked Responses to Them (Contd.)