Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 8-43
PROGRAMMING WITH THE X87 FPU
The inexact-result exception flag (PE) is bit 5 of the x87 FPU status word, and the
mask bit (PM) is bit 5 of the x87 FPU control word.
If the inexact-result exception is masked when an inexact-result condition occurs and
a numeric overflow or underflow condition has not occurred, the x87 FPU handles the
exception as describe in Section 4.9.1.6, “Inexact-Result (Precision) Exception (#P),”
with one additional action. The C1 (round-up) bit in the x87 FPU status word is set to
indicate whether the inexact result was rounded up (C1 is set) or “not rounded up”
(C1 is cleared). In the “not rounded up” case, the least-significant bits of the inexact
result are truncated so that the result fits in the destination format.
If the inexact-result exception is not masked when an inexact result occurs and
numeric overflow or underflow has not occurred, the x87 FPU handles the exception
as described in the previous paragraph and, in addition, invokes a software exception
handler.
If an inexact result occurs in conjunction with numeric overflow or underflow, the x87
FPU carries out one of the following operations:
• If an inexact result occurs in conjunction with masked overflow or underflow, the
OE or UE flag and the PE flag are set and the result is stored as described for the
overflow or underflow exceptions (see Section 8.5.4, “Numeric Overflow
Exception (#O),” or Section 8.5.5, “Numeric Underflow Exception (#U)”). If the
inexact result exception is unmasked, the x87 FPU also invokes a software
exception handler.
• If an inexact result occurs in conjunction with unmasked overflow or underflow
and the destination operand is a register, the OE or UE flag and the PE flag are
set, the result is stored as described for the overflow or underflow exceptions
(see Section 8.5.4, “Numeric Overflow Exception (#O),” or Section 8.5.5,
“Numeric Underflow Exception (#U)”) and a software exception handler is
invoked.
If an unmasked numeric overflow or underflow exception occurs and the destination
operand is a memory location (which can happen only for a floating-point store), the
inexact-result condition is not reported and the C1 flag is cleared.
8.6 X87 FPU EXCEPTION SYNCHRONIZATION
Because the integer unit and x87 FPU are separate execution units, it is possible for
the processor to execute floating-point, integer, and system instructions concur-
rently. No special programming techniques are required to gain the advantages of
concurrent execution. (Floating-point instructions are placed in the instruction
stream along with the integer and system instructions.) However, concurrent execu-
tion can cause problems for floating-point exception handlers.
This problem is related to the way the x87 FPU signals the existence of unmasked
floating-point exceptions. (Special exception synchronization is not required for