Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 8-45
PROGRAMMING WITH THE X87 FPU
lutely insure that any exceptions emanating from the FSQRT instruction are handled
(for example, prior to a procedure call), a WAIT instruction can be placed directly
after the FSQRT instruction.
Note that some floating-point instructions (non-waiting instructions) do not check for
pending unmasked exceptions (see Section 8.3.11, “x87 FPU Control Instructions”).
They include the FNINIT, FNSTENV, FNSAVE, FNSTSW, FNSTCW, and FNCLEX instruc-
tions. When an FNINIT, FNSTENV, FNSAVE, or FNCLEX instruction is executed, all
pending exceptions are essentially lost (either the x87 FPU status register is cleared
or all exceptions are masked). The FNSTSW and FNSTCW instructions do not check
for pending interrupts, but they do not modify the x87 FPU status and control regis-
ters. A subsequent “waiting” floating-point instruction can then handle any pending
exceptions.
8.7 HANDLING X87 FPU EXCEPTIONS IN SOFTWARE
The x87 FPU in Pentium and later IA-32 processors provides two different modes of
operation for invoking a software exception handler for floating-point exceptions:
native mode and MS-DOS compatibility mode. The mode of operation is selected
when CR0.NE[bit 5] is CR0. (See Chapter 2, “System Architecture Overview,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for
more information about the NE flag.)
8.7.1 Native Mode
The native mode for handling floating-point exceptions is selected by setting
CR0.NE[bit 5] to 1. In this mode, if the x87 FPU detects an exception condition while
executing a floating-point instruction and the exception is unmasked (the mask bit
for the exception is cleared), the x87 FPU sets the flag for the exception and the ES
flag in the x87 FPU status word. It then invokes the software exception handler
through the floating-point-error exception (#MF, vector 16), immediately before
execution of any of the following instructions in the processor’s instruction stream:
• The next floating-point instruction, unless it is one of the non-waiting instructions
(FNINIT, FNCLEX, FNSTSW, FNSTCW, FNSTENV, and FNSAVE).
• The next WAIT/FWAIT instruction.
• The next MMX instruction.
If the next floating-point instruction in the instruction stream is a non-waiting
instruction, the x87 FPU executes the instruction without invoking the software
exception handler.
8.7.2 MS-DOS* Compatibility Sub-mode
If CR0.NE[bit 5] is 0, the MS-DOS compatibility mode for handling floating-point
exceptions is selected. In this mode, the software exception handler for floating-
point exceptions is invoked externally using the processor’s FERR#, INTR, and
IGNNE# pins. This method of reporting floating-point errors and invoking an excep-